S70FL01GS
1 Gbit (128 Mbyte) 3.0V SPI Flash
Features
CMOS 3.0V Core
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
– AutoBoot – power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock
systems
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles, minimum
Data Retention
– 20 Year Data Retention, minimum
Security Features
One Time Program (OTP) array of 2048 bytes
Block Protection
– Status Register bits to control protection against program
or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress
®
65 nm MirrorBit
®
Technology with Eclipse
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
Temperature Range / Grade:
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
– 16-lead SOIC (300 mils)
– BGA-24, 8
6 mm
– 5
5 ball (ZSA024) footprint
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, refer to the discrete die datasheet provided in the
Affected Documents/Related Documents
table.
Affected Documents/Related Documents
Document Title
S25FL512S 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Datasheet
Publication Number
001-98284
Cypress Semiconductor Corporation
Document Number: 001-98295 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 03, 2018
S70FL01GS
Contents
1.
2.
3.
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.
6.
7.
8.
9.
Block Diagram..............................................................
3
Connection Diagrams..................................................
4
Input/Output Summary
................................................ 5
Device Operations
.......................................................
Programming .................................................................
Simultaneous Die Operation ..........................................
Sequential Reads...........................................................
Sector/Bulk Erase ..........................................................
Status Registers.............................................................
Configuration Register ...................................................
Bank Address Register ..................................................
Security and DDR Registers ..........................................
Block Protection .............................................................
6
6
6
6
6
6
6
6
6
6
10. SDR AC Characteristics
............................................. 10
10.1 DDR AC Characteristics ............................................... 11
10.2 Capacitance Characteristics ......................................... 11
11. Ordering Information
.................................................. 12
11.1 Valid Combinations — Standard................................... 13
11.2 Valid Combinations — Automotive Grade /
AEC-Q100 .................................................................... 13
12.
12.1
12.2
12.3
Other Resources
......................................................... 14
Cypress Flash Memory Roadmap ................................ 14
Links to Software .......................................................... 14
Links to Application Notes............................................. 14
Read Identification (RDID)...........................................
7
RESET#
......................................................................... 7
Versatile I/O Power Supply (V
IO
).................................
7
DC Characteristics.......................................................
8
AC Test Conditions......................................................
9
13. Physical Diagram
........................................................ 15
13.1 SOIC 16 Lead, 300-mil Body Width .............................. 15
13.2 24-Ball BGA 8 x 6 mm (ZSA024) .................................. 16
14. Revision History..........................................................
17
Sales, Solutions, and Legal Information .......................... 19
Worldwide Sales and Design Support ........................... 19
Products ........................................................................ 19
PSoC® Solutions .......................................................... 19
Cypress Developer Community ..................................... 19
Technical Support ......................................................... 19
Document Number: 001-98295 Rev. *N
Page 2 of 19
S70FL01GS
1. Block Diagram
SI/IO0
WP#/IO2
HOLD#/IO3
S I/IO 0
WP#/IO2
S O /IO 1
H O LD #/IO 3
SO/IO1
SCK
CS#1
SCK
CS#
FL512S
Flash
Memory
VSS
VSS
VCC
VCC
S I/IO 0
WP#/IO2
H O LD #/IO 3
S O /IO 1
SCK
CS#2
CS#
FL512S
Flash
Memory
VSS
VCC
Document Number: 001-98295 Rev. *N
Page 3 of 19
S70FL01GS
2.
Connection Diagrams
Figure 1. 16-Pin Plastic Small Outline Package (SO)
HOLD#/IO3
VCC
RESET#
DNU
DNU
CS2#
CS1#
SO/IO1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCK
SI/IO0
VIO/RFU
NC
DNU
DNU
VSS
WP#/IO2
Figure 2. 24-Ball BGA, 5 x 5 Ball Footprint (ZSA024), Top View
1
A
DNU
B
DNU
C
DNU
D
DNU
E
DNU
DNU
DNU
VIO/RFU
DNU
SO/IO1
SI/IO0 HOLD#/IO3 DNU
CS1#
RFU
WP#/IO2
RFU
SCK
VSS
VCC
RFU
CS2#
RESET#
RFU
2
3
4
5
Note:
1. V
IO
is not supported in the S70FL01GS device and is RFU. Refer to
Section 7.
for more details.
Document Number: 001-98295 Rev. *N
Page 4 of 19
S70FL01GS
3.
Input/Output Summary
Type
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Supply
Supply
Supply
Unused
Description
Hardware Reset:
Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used.
Serial Clock.
Chip Select.
FL512S #1.
Chip Select.
FL512S #2.
Serial Input
for single bit data commands or IO0 for Dual or Quad commands.
Serial Output
for single bit data commands. IO1 for Dual or Quad commands.
Write Protect
when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up
resistor and may be left unconnected in the host system if not used for Quad commands.
Hold
(pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The
signal has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad commands.
Core Power Supply.
Versatile I/O Power Supply. Note:
V
IO
is not supported in the S70FL01GS device. Refer to
Section 7.
for more details.
Ground.
Not Connected.
No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for routing
space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC
must not have voltage levels higher than V
CC
.
Reserved for Future Use.
No device internal signal is currently connected to the package
connector but there is potential future use of the connector for a signal. It is recommended to not
use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.
Do Not Use.
A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for connection
to any host system signal. Any DNU signal related function will be inactive when the signal is at
V
IL
. The signal has an internal pull-down resistor and may be left unconnected in the host system
or may be tied to V
SS
. Do not use these connections for PCB signal routing channels. Do not
connect any host system signal to this connection.
Table 2. Signal List
Signal Name
RESET#
SCK
CS1#
CS2#
SI / IO0
SO / IO1
WP# / IO2
HOLD# / IO3
V
CC
V
IO
V
SS
NC
RFU
Reserved
DNU
Reserved
Document Number: 001-98295 Rev. *N
Page 5 of 19
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