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Abridged Data Sheet
DS2460
SHA-1 Coprocessor with EEPROM
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2460 SHA-1 Coprocessor with EEPROM is a
hardware implementation of the ISO/IEC 10118-3
Secure Hash Algorithm (SHA-1), eliminating the need
to develop software to perform the complex SHA
computation required for authenticating SHA devices
and for performing the validation of digitally signed
service data. The DS2460 communicates with a
microcontroller through the popular I²C interface.
Applications include hosts of access control and
electronic payment systems for token authentication
and service data validation as well as generation of
one-time-use encryption keys for short message
encryption and decryption for messages not exceed-
ing the length of a SHA-1 result, which is 20 bytes.
FEATURES
Dedicated Hardware-Accelerated SHA Engine
for Generating SHA-1 MACs
112 Bytes User EEPROM for Storing End
Equipment Property Data
I²C Host Interface, Supports 100kHz and 400kHz
Communication Speeds
Three Address Inputs for I²C Address
Assignment
Single-Byte to 8-Byte EEPROM Write
Sequences
64-Bit Unique Registration Number
EEPROM Endurance: 200k Cycles per 8-Byte
Block at 25°C
10ms max EEPROM Write Cycle
Wide Operating Range: 2.7V to 5.5V,
-40°C to +85°C
±4kV IEC 1000-4-2 ESD Protection Level on All
Pins
8-Pin SO (150 mils) Package
APPLICATIONS
License Management
Secure Feature Control
System Authentication
Clone Prevention
Door Locks
Utility Meters
ORDERING INFORMATION
PART
DS2460S
DS2460S/T&R
DS2460S+
DS2460S+T&R
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 SO (150 mils)
8 SO (150 mils)
8 SO (150 mils)
8 SO (150 mils)
TYPICAL OPERATING CIRCUIT
V
CC
R
P
V
CC
SDA
SCL
R
P
+Denotes a lead(Pb)-free/RoHS-compliant package.
Request full data sheet at:
www.maxim-ic.com/fullds/DS2460
V
CC
SDA
SCL
AD0
AD1
µC
GND
PIN CONFIGURATION
AD0
AD1
AD2
GND
1
2
3
4
8
7
6
5
V
CC
SCL
SDA
N.C.
AD2
GND
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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Abridged Data Sheet
DS2460
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Maximum Current Into Any Pin
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Lead Temperature (soldering 10s)
Soldering Temperature (reflow)
-0.5V, +6V
±20mA
-40°C to +85°C
+150°C
-55°C to +125°C
+300°C
+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS
(-40°C to +85°C, see Note 1)
PARAMETER
Supply Voltage
Standby Current
Operating Current
Programming Current
SHA-1 Computation Current
SHA-1 Engine
SHA-1 Computation Time
EEPROM
Programming Time
Endurance
Data Retention
I²C-Pins (Note 7) See Figure 6
LOW Level Input Voltage
HIGH Level Input Voltage
Hysteresis of Schmitt Trigger
Inputs
LOW Level Output Voltage at
4mA Sink Current
Output Fall Time from V
Ihmin
to
V
ILmax
with a Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes that are
Suppressed by the Input Filter
Input Current Each I/O Pin with
an Input Voltage Between
0.1V
CCmax
and 0.9V
CCmax
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
V
IL
V
IH
V
hys
V
OL
t
of
t
SP
I
i
C
i
f
SCL
t
HD:STA
t
LOW
t
HIGH
2 of 9
(Note 9)
SDA and SCL pins only
(Note 9)
(Notes 8, 10)
(Notes 8, 9)
0
0.6
1.3
0.6
-10
20 +
0.1Cb
(Note 8)
(Notes 8, 9)
(Note 9)
-0.5
0.7 ×
V
CC
0.05 ×
V
CC
0.3 ×
V
CC
V
CC
+
0.5V
V
V
V
0.4
250
50
10
10
400
V
ns
ns
µA
pF
kHz
µs
µs
µs
t
PROG
N
CYCLE
t
RET
At +25°C (Notes 2, 3)
At +85°C (Notes 4, 5, 6)
200k
40
years
10
ms
t
SHA
See full version of data sheet
SYMBOL
V
CC
I
CCS
I
CCA
I
PROG
I
SHA
CONDITIONS
Bus idle
Bus idle, +25°C
Bus active at 400kHz
(Note 9)
See full version of data sheet
MIN
2.7
TYP
MAX
5.5
3
UNITS
V
µA
µA
µA
mA
ms
250
500
1
500
1000
Abridged Data Sheet
PARAMETER
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
SYMBOL
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
B
(Note 14)
(Notes 11, 12)
(Note 13)
CONDITIONS
MIN
0.6
0.9
100
0.6
1.3
400
TYP
MAX
DS2460
UNITS
µs
µs
ns
µs
µs
pF
Note 14:
Specification at -40°C is guaranteed by design and characterization only and not production tested.
Write-cycle endurance is degraded as T
A
increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
A
increases.
Guaranteed by 100% production test at elevated temperature for a shorter amount of time;
equivalence of this production test to data sheet limit at operating temperature range is established by
reliability testing.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term
storage at elevated temperatures is not recommended; the device can lose its write capability after 10
years at +125°C or 40 years at +85°C.
All values are referred to V
IHmin
and V
ILmax
levels.
Applies to SDA, SCL, AD2, AD1, AD0.
Guaranteed by simulation only, not production tested.
I/O pins of the DS2460 do not obstruct the SDA and SCL lines if V
CC
is switched off.
The DS2460 provides a hold time of at least 300ns for the SDA signal (referred to the V
IHmin
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
t
SU:DAT
250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + t
SU:DAT
= 1000 + 250 = 1250ns (according to the
standard-mode I²C-bus specification) before the SCL line is released.
C
B
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I²C-Bus Specification v2.1 are allowed.
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
NAME
AD0
AD1
AD2
GND
NC
SDA
SCL
V
CC
FUNCTION
I²C Address Inputs; must be tied to VCC or GND. These inputs determine the I²C slave
address of the device, see Figure 5.
Ground Reference
Not Connected
I²C Serial Data Input/Output; must be tied to V
CC
through a pullup resistor.
I²C Serial Clock Input; must be tied to V
CC
through a pullup resistor.
Power Supply Input
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS2460. The DS2460 communicates with a host processor through its I²C bus interface in standard-mode or in
fast-mode. The logic state of three address pins determines the I²C slave address of the DS2460, allowing up to 8
devices to operate on the same bus segment without requiring a hub. For more information (including Figure 2)
refer to the full version of the data sheet.
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Abridged Data Sheet
DS2460
Figure 1. Block Diagram
64-bit Unique
Number
MAC Output
Buffer
64-Byte Input
Buffer
Command Buffer
and SHA-1
Engine Control
SCL
SDA
ADx
2-wire
Function
Control
SHA-1
Engine
S-Secret
E-Secret1
E-Secret2
8-Byte EEPROM
Write Buffer
E-Secret3
112-Byte User
EEPROM
DETAILED REGISTER DESCRIPTION
For this section (including Figure 3) please refer to the full version of the data sheet.
DEVICE OPERATION
The typical use of the DS2460 in an application involves writing, reading, running the SHA-1 engine, transferring
secrets and comparing MACs. All these activities are controlled through the I²C serial interface.
I²C Serial Communication Interface
General Characteristics
The I²C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirec-
tional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both
lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to
perform the wired-AND function. Data on the I²C bus can be transferred at rates of up to 100kbps in the Standard-
mode, up to 400kbps in the Fast-mode. The DS2460 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” To be individually accessed, each device must have a slave address that does not conflict with other
devices on the bus.
Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of data bytes
transferred between START and STOP (Figure 4). Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
4 of 9
Abridged Data Sheet
DS2460
Slave Address
The slave address to which the DS2460 responds is shown in Figure 5. The logic states at the address pins AD0,
AD1 and AD2 determine the value of the address bits A0, A2, and A4. The address pins allow the device to
respond to one of eight possible slave addresses. The slave address is part of the slave-address/control byte. The
last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will
flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access
mode).
Figure 4. I²C Protocol Overview
MS-bit
SDA
Slave Address
Acknowledgment
from Receiver
Repeated if more bytes
are transferred
R/
W
ACK
bit
ACK
bit
SCL
Idle
START
Condition
1
2
6
7
8
9
ACK
1
2
8
9
ACK
STOP Condition
Repeated START
Condition
Figure 5. DS2460 Slave Address
7-Bit Slave Address
A6
1
A5
0
A4
AD2
A3
0
A2
AD1
A1
0
A0
AD0 R/W
Most Signi-
ficant Bit
AD2, AD1, AD0
Pin States
Determines
Read or Write
I²C Definitions
The following terminology is commonly used to describe I²C data transfers. The timing references are defined in
Figure 6.
Bus Idle or Not Busy
Both, SDA and SCL, are inactive and in their logic HIGH states.
START Condition
To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. A valid slave address must be
sent by the master and acknowledged by the slave before subsequent START conditions are recognized.
STOP Condition
To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH. A valid slave address must be sent by the
master and acknowledged by the slave before subsequent STOP conditions are recognized.
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