19-5640; Rev 11/10
DS1245W
3.3V 1024k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Replaces 128k x 8 volatile static RAM,
EEPROM or Flash memory
Unlimited write cycles
Low-power CMOS
Read and write access times of 100ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Optional industrial temperature range of
-40°C to +85°C, designated IND
JEDEC standard 32-pin DIP package
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-PIN Encapsulated Package
740-Mil Extended
NC
A15
A16
NC
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND V
BAT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
PIN DESCRIPTION
A0 - A16
DQ0 - DQ7
CE
WE
OE
V
CC
GND
NC
1 of 10
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+3.3V)
- Ground
- No Connect
DS1245W
DESCRIPTION
The DS1245W 3.3V 1024k Nonvolatile SRAM is a 1,048,576-bit, fully static, nonvolatile SRAM
organized as 131,072 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1245W devices can be used in place of existing 128k
x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245W devices in
the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1245W executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 17 address inputs
(A
0
- A
16
) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
satisfied, then data access must be measured from the later occurring signal (
CE
or
OE
) and the limiting
parameter is either t
CO
for
CE
or t
OE
for
OE
rather than address access.
WRITE MODE
The DS1245W executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
inputs are stable. The later occurring falling edge of
CE
or
WE
will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (t
WR
)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1245W provides full functional capability for V
CC
greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V
CC
without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V
CC
rises above approximately 2.5 volts, the power
switching circuit connects external V
CC
to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after V
CC
exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1245W device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When V
CC
is first applied at a level greater than 3.0 volts, the lithium energy source
is enabled for battery back-up operation.
PACKAGES
The DS1245W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
2 of 10
DS1245W
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
Industrial:
Storage Temperature Range
EDIP
PowerCap
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow, PowerCap)
Note:
EDIP is wave or hand soldered only.
-0.3V to +4.6V
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
+260°C
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Logic 1
Logic 0
SYMBOL
V
CC
V
IH
V
IL
MIN
3.0
2.2
0.0
TYP
3.3
MAX
3.6
V
CC
0.4
(t
A
: See Note 10)
UNITS
V
V
V
NOTES
DC ELECTRICAL CHARACTERISTICS
0.3V)
PARAMETER
Input Leakage Current
I/O Leakage Current
CE
≥
V
IH
≤
V
CC
Output Current @ 2.2V
Output Current @ 0.4V
Standby Current
CE
=2.2V
Standby Current
CE
=V
CC
-0.2V
Operating Current
Write Protection Voltage
SYMBOL
I
IL
I
IO
I
OH
I
OL
I
CCS1
I
CCS2
I
CCO1
V
TP
(t
A
: See Note 10) (V
CC
=3.3V
MIN
-1.0
-1.0
-1.0
2.0
50
30
2.8
2.9
250
150
50
3.0
TYP
MAX
+1.0
+1.0
UNITS
µA
µA
mA
mA
µA
µA
mA
V
NOTES
CAPACITANCE
(t
A
=25
C)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
5
5
MAX
10
10
UNITS
pF
pF
NOTES
4 of 10
FPGA/CPLD
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