GDLXT9785MBCD0 datasheet, PDF - EEWORLD Datasheet

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GDLXT9785MBCD0: DescriptionInterface Circuit, PBGA196, PLASTIC, BGA-196; CategoryTelecom circuit; File Size4MB，234 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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GDLXT9785MBCD0 Overview

Interface Circuit, PBGA196, PLASTIC, BGA-196

GDLXT9785MBCD0 Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	BGA
package instruction	BGA,
Contacts	196
Reach Compliance Code	unknown
Is Samacsys	N
JESD-30 code	S-PBGA-B196
length	15 mm
Number of functions	1
Number of terminals	196
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	2 mm
Nominal supply voltage	2.5 V
surface mount	YES
Telecom integrated circuit types	INTERFACE CIRCUIT
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm
Base Number Matches	1

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Intel

LXT9785 and LXT9785E Advanced

8-Port 10/100 Mbps PHY Transceivers

Datasheet

The Intel

LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting

IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/

Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media

Independent Interface (RMII) for switching and other independent port applications. The

LXT9785 and LXT9785E are identical except for the IP telephony features included in the

LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects

Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The

system uses the information collected by the LXT9785E to apply power if the DTE at the far end

requires power over the cable, such as an IP telephone.

Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled

Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps

(10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports

100 Mbps (100BASE-FX) Ethernet over fiber-optic media.

The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices

support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a

single 2.5 V power supply.

Applications

Enterprise switches

IP telephony switches

Storage Area Networks

Multi-port Network Interface Cards (NICs)

Product Features

Eight IEEE 802.3-compliant 10BASE-T or

100BASE-TX ports with integrated filters.

100BASE-FX fiber-optic capability on all

ports.

2.5 V operation.

Low power consumption; 250 mW per port

typical.

Multiple RMII or SMII/SS-SMII ports for

independent PHY port operation.

Auto MDI/MDIX crossover capability.

Proprietary Optimal Signal Processing™

architecture improves SNR by 3 dB over

ideal analog filters.

Optimized for dual-high stacked RJ-45

applications.

MDIO sectionalization into 2x4 or 1x8

configurations.

Supports both auto-negotiation systems and

legacy systems without auto-negotiation

capability.

Robust baseline wander correction.

Configurable through the MDIO port or

external control pins.

JTAG boundary scan.

208-pin PQFP: LXT9785HC,

LXT9785EHC, LXT9785HE.

241-ball BGA: LXT9785BC,

LXT9785EBC.

196-ball BGA: LXT9785MBC (includes

DTE detection similar to the LXT9785E)

DTE detection for remote powering

applications (LXT9785E and

LXT9785MBC only).

Extended temperature operation of -40

to +85

C (LXT9785E only).

Document Number: 249241

Revision Number: 010

Revision Date: 30-May-2006

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL

PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT.

Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

LXT9785 and Intel

LXT9785E PHY Transceivers may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Document Number: 249241

Revision Number: 010

Revision Date: 30-May-2006

Contents

1.0

Introduction..................................................................................................................................17

1.1

1.2

2.0

3.0

What You Will Find in This Document ................................................................................ 17

Related Documents ............................................................................................................ 17

Block Diagram

............................................................................................................................. 18

Pin/Ball Assignments and Signal Descriptions

........................................................................ 19

3.1

PQFP Pin Assignments ...................................................................................................... 19

3.1.1 PQFP Pin Assignments – RMII Configuration ....................................................... 20

3.1.2 PQFP Pin Assignments – SMII Configuration........................................................ 25

3.1.3 PQFP Pin Assignments – SS-SMII Configuration.................................................. 30

PQFP Signal Descriptions .................................................................................................. 35

3.2.1 Signal Name Conventions .....................................................................................35

3.2.2 PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations.................. 35

BGA23 Ball Assignments.................................................................................................... 50

3.3.1 RMII BGA23 Ball List ............................................................................................. 51

3.3.2 SMII BGA23 Ball List ............................................................................................. 61

3.3.3 SS-SMII BGA23 Ball List ....................................................................................... 71

BGA23 Signal Descriptions ................................................................................................ 81

3.4.1 Signal Name Conventions .....................................................................................81

3.4.2 Signal Descriptions – RMII, SMII, and SS-SMII Configurations............................. 81

BGA15 Ball Assignments.................................................................................................... 98

3.5.1 BGA15 Ball List...................................................................................................... 99

BGA15 Signal Descriptions .............................................................................................. 108

3.6.1 Signal Name Conventions ...................................................................................108

3.6.2 Signal Descriptions – SMII and SS-SMII Configurations ..................................... 108

3.2

3.3

3.4

3.5

3.6

4.0

Functional Description..............................................................................................................

115

4.1

Introduction ....................................................................................................................... 115

4.1.1 OSP™ Architecture ............................................................................................. 115

4.1.2 Comprehensive Functionality .............................................................................. 116

4.1.2.1 Sectionalization .................................................................................... 116

Interface Descriptions ....................................................................................................... 116

4.2.1 10/100 Network Interface..................................................................................... 116

4.2.1.1 Twisted-Pair Interface .......................................................................... 117

4.2.1.2 MDI Crossover (MDIX)......................................................................... 118

4.2.1.3 Fiber Interface ...................................................................................... 118

Media Independent Interface (MII) Interfaces ................................................................... 118

4.3.1 Global MII Mode Select ....................................................................................... 118

4.3.2 Internal Loopback ................................................................................................ 119

4.3.3 RMII Data Interface.............................................................................................. 119

4.3.4 Serial Media Independent Interface (SMII) and Source Synchronous- Serial Media

Independent Interface (SS-SMII)120

4.3.4.1 SMII Interface....................................................................................... 120

4.3.4.2 Source Synchronous-Serial Media Independent Interface .................. 120

4.3.5 Configuration Management Interface .................................................................. 120

4.3.6 MII Isolate ............................................................................................................ 120

4.2

4.3

Datasheet

Document Number: 249241

Revision Number: 010

Revision Date: 30-May-2006

Contents

4.4

4.5

4.6

4.7

4.8

4.9

4.3.7 MDIO Management Interface .............................................................................. 120

4.3.8 MII Sectionalization.............................................................................................. 122

4.3.9 MII Interrupts........................................................................................................ 122

4.3.10 Global Hardware Control Interface ...................................................................... 123

4.3.11 FIFO Initial Fill Values.......................................................................................... 123

Operating Requirements................................................................................................... 124

4.4.1 Power Requirements ........................................................................................... 124

4.4.2 Clock/SYNC Requirements ................................................................................. 124

4.4.2.1 Reference Clock .................................................................................. 124

4.4.2.2 TxCLK Signal (SS-SMII only)............................................................... 124

4.4.2.3 TxSYNC Signal (SMII/SS-SMII)........................................................... 124

4.4.2.4 RxSYNC Signal (SS-SMII only) ........................................................... 124

4.4.2.5 RxCLK Signal (SS-SMII Only) ............................................................. 125

Initialization ....................................................................................................................... 125

4.5.1 MDIO Control Mode............................................................................................. 125

4.5.2 Hardware Control Mode....................................................................................... 125

4.5.3 Power-Down Mode .............................................................................................. 126

4.5.3.1 Global (Hardware) Power Down .......................................................... 127

4.5.3.2 Port (Software) Power Down ............................................................... 127

4.5.4 Reset ................................................................................................................... 127

4.5.5 Hardware Configuration Settings......................................................................... 128

Link Establishment............................................................................................................ 128

4.6.1 Auto-Negotiation .................................................................................................. 128

4.6.1.1 Base Page Exchange .......................................................................... 128

4.6.1.2 Manual Next Page Exchange .............................................................. 129

4.6.1.3 Controlling Auto-Negotiation ................................................................ 129

4.6.1.4 Link Criteria.......................................................................................... 129

4.6.1.5 Parallel Detection................................................................................. 129

4.6.1.6 Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced

Speed Mode130

Serial MII Operation.......................................................................................................... 130

4.7.1 SMII Reference Clock.......................................................................................... 134

4.7.2 TxSYNC Pulse (SMII/SS-SMII)............................................................................ 134

4.7.3 Transmit Data Stream.......................................................................................... 134

4.7.3.1 Transmit Enable................................................................................... 134

4.7.3.2 Transmit Error ...................................................................................... 134

4.7.4 Receive Data Stream........................................................................................... 135

4.7.4.1 Carrier Sense....................................................................................... 135

4.7.4.2 Receive Data Valid .............................................................................. 135

4.7.4.3 Receive Error ....................................................................................... 135

4.7.4.4 Receive Status Encoding..................................................................... 135

4.7.5 Collision ............................................................................................................... 135

4.7.6 Source Synchronous-Serial Media Independent Interface .................................. 136

RMII Operation ................................................................................................................. 140

4.8.1 RMII Reference Clock.......................................................................................... 140

4.8.2 Transmit Enable................................................................................................... 141

4.8.3 Carrier Sense & Data Valid.................................................................................. 141

4.8.4 Receive Error....................................................................................................... 141

4.8.5 Out-of-Band Signaling ......................................................................................... 141

4.8.6 4B/5B Coding Operations .................................................................................... 141

100 Mbps Operation ......................................................................................................... 144

Datasheet

Document Number: 249241

Revision Number: 010

Revision Date: 30-May-2006

Contents

4.10

4.11

4.12

4.13

4.14

100BASE-X Network Operations ......................................................................... 144

100BASE-X Protocol Sublayer Operations.......................................................... 144

4.9.2.1 PCS Sublayer ...................................................................................... 144

4.9.3 PMA Sublayer ......................................................................................................146

4.9.3.1 Link ......................................................................................................147

4.9.3.2 Link Failure Override............................................................................147

4.9.3.3 Carrier Sense/Data Valid (RMII) .......................................................... 147

4.9.3.4 Carrier Sense (SMII) ............................................................................147

4.9.3.5 Receive Data Valid (SMII).................................................................... 147

4.9.3.6 Twisted-Pair PMD Sublayer ................................................................. 148

4.9.3.7 Fiber PMD Sublayer............................................................................. 148

10 Mbps Operation ........................................................................................................... 149

4.10.1 Preamble Handling .............................................................................................. 149

4.10.2 Dribble Bits .......................................................................................................... 150

4.10.3 Link Test .............................................................................................................. 150

4.10.3.1 Link Failure ..........................................................................................150

4.10.4 Jabber ..................................................................................................................150

DTE Discovery Process .................................................................................................... 151

4.11.1 Definitions ............................................................................................................ 151

4.11.2 Interaction between Processor, MAC, and PHY ..................................................152

4.11.3 Management Interface and Control .....................................................................152

4.11.4 DTE Discovery Process Flow .............................................................................. 153

4.11.5 DTE Discovery Behavior...................................................................................... 154

Monitoring Operations ......................................................................................................156

4.12.1 Monitoring Auto-Negotiation ................................................................................ 156

4.12.2 Per-Port LED Driver Functions ............................................................................156

4.12.3 Out-of-Band Signaling ......................................................................................... 157

4.12.4 Boundary Scan Interface ..................................................................................... 158

4.12.5 State Machine ......................................................................................................158

4.12.6 Instruction Register .............................................................................................. 158

4.12.7 Boundary Scan Register ...................................................................................... 158

Cable Diagnostics Overview ............................................................................................. 159

4.13.1 Features............................................................................................................... 159

4.13.2 Operation .............................................................................................................159

4.13.2.1 Short and Long Cable Testing Requirements ......................................159

4.13.2.2 Precision .............................................................................................. 159

4.13.3 Implementation Considerations ........................................................................... 160

4.13.4 Basic Implementation ..........................................................................................160

Link Hold-Off Overview ..................................................................................................... 161

4.14.1 Features............................................................................................................... 161

4.14.2 Operation .............................................................................................................162

4.9.1

4.9.2

5.0

Application Information

............................................................................................................ 164

5.1

5.2

Design Recommendations................................................................................................ 164

General Design Guidelines ...............................................................................................164

5.2.1 Power Supply Filtering ......................................................................................... 164

5.2.2 Power and Ground Plane Layout Considerations................................................ 165

5.2.2.1 Chassis Ground ...................................................................................165

5.2.3 MII Terminations .................................................................................................. 165

5.2.4 Twisted-Pair Interface ..........................................................................................165

5.2.4.1 Magnetic Requirements .......................................................................166

Datasheet

Document Number: 249241

Revision Number: 010

Revision Date: 30-May-2006

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