Changes to Ordering Guide .......................................................... 27
2/2015—Revision 0: Initial Version
Rev. E | Page 2 of 27
Data Sheet
SPECIFICATIONS
ADP5071
PVIN1 = PVIN2 = PVINSYS = 2.85 V to 15 V, V
POS
= 15 V, V
NEG
= −15 V, f
SW
= 1200 kHz, T
J
= −40°C to +125°C for minimum/maximum
specifications, and T
A
= 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
PVIN1, PVIN2, PVINSYS (Total)
Shutdown Current
UVLO
System UVLO Threshold
Rising
Falling
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
Symbol
V
IN
Min
2.85
Typ
Max
15
Unit
V
Test Conditions/Comments
PVIN1, PVIN2, PVINSYS
I
Q
I
SHDN
3.5
5
4.0
10
mA
µA
No switching, EN1 = EN2 = high,
PVIN1 = PVIN2 = PVINSYS = 5 V
No switching, EN1 = EN2 = low,
PVIN1 = PVIN2 = PVINSYS = 5 V
PVINSYS
V
UVLO_RISING
V
UVLO_FALLING
V
HYS_1
f
SW
2.5
2.8
2.55
0.25
1.200
2.400
2.85
V
V
V
MHz
MHz
SYNC/FREQ = low
SYNC/FREQ = high (connect to
VREG)
1.130
2.240
1.270
2.560
SYNC/FREQ Input
Input Clock Range
Input Clock Minimum On Pulse Width
Input Clock Minimum Off Pulse Width
Input Clock High Logic
Input Clock Low Logic
PRECISION ENABLING (EN1, EN2)
High Level Threshold
Low Level Threshold
Shutdown Mode
Pull-Down Resistance
INTERNAL REGULATOR
VREG Output Voltage
BOOST REGULATOR
Feedback Voltage
Feedback Voltage Accuracy
Feedback Bias Current
Overvoltage Protection Threshold
Load Regulation
Line Regulation
Error Amplifier (EA) Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage
Input Disconnect Switch On Resistance
Current-Limit Threshold
Minimum On Time
Minimum Off Time
f
SYNC
t
SYNC_MIN_ON
t
SYNC_MIN_OFF
V
H (SYNC)
V
L (SYNC)
V
TH_H
V
TH_L
V
TH_S
R
EN
V
REG
V
FB1
1.000
100
100
0.4
1.125
1.025
0.4
1.15
1.05
2.600
1.3
MHz
ns
ns
V
V
V
V
V
MΩ
V
V
%
%
µA
V
%/mA
%/V
µA/V
mΩ
V
mΩ
A
ns
ns
1.175
1.075
Internal circuitry disabled to
achieve ISHDN
1.48
4.25
0.8
−0.5
−1.5
+0.5
+1.5
0.1
0.86
0.0003
0.002
270
300
175
39
210
2.2
50
25
330
T
J
= 25°C
T
J
= −40°C to +125°C
At FB1 pin
I
LOAD1 1
= 5 mA to 150 mA
V
PVIN1
= 2.85 V to 14.5 V, I
LOAD11
=
50 mA
I
FB1
V
OV1
∆V
FB1
/I
LOAD1
∆V
FB1
/V
PVIN1
g
M1
R
DS (ON) BOOST
V
DS (MAX) BOOST
R
DS (ON) INBK
I
LIM (BOOST)
2.0
2.4
Rev. E | Page 3 of 27
ADP5071
Parameter
INVERTING REGULATOR
Reference Voltage
Reference Voltage Accuracy
Feedback Voltage
Feedback Voltage Accuracy
Feedback Bias Current
Overvoltage Protection Threshold
Load Regulation
Line Regulation
EA Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage
Current-Limit Threshold
Minimum On Time
Minimum Off Time
SOFT START
Soft Start Timer for Boost and Inverting
Regulators
Hiccup Time
THERMAL SHUTDOWN
Threshold
Hysteresis
1
Data Sheet
Symbol
V
REF
−0.5
−1.5
V
REF
− V
FB2
−0.5
−1.5
I
FB2
V
OV2
∆(V
REF
− V
FB2
)/
I
LOAD2
∆(V
REF
− V
FB2
)/
V
PVIN2
g
M2
R
DS (ON) INVERTER
V
DS (MAX) INVERTER
I
LIM (INVERTER)
0.74
0.0004
0.003
270
300
350
39
1320
60
50
4
32
8 × t
SS
150
15
330
0.8
+0.5
+1.5
0.1
Min
Typ
1.60
+0.5
+1.5
Max
Unit
V
%
%
V
%
%
µA
V
%/mA
%/V
µA/V
mΩ
V
mA
ns
ns
ms
ms
ms
°C
°C
SS = open
SS resistor = 50 kΩ to GND
Test Conditions/Comments
T
J
= 25°C
T
J
= −40°C to +125°C
T
J
= 25°C
T
J
= −40°C to +125°C
At FB2 pin after soft start has
completed
I
LOAD21
= 5 mA to 75 mA
V
PVIN2
= 2.85 V to 14.5 V, I
LOAD21
=
25 mA
1200
1440
t
SS
t
HICCUP
T
SHDN
T
HYS
I
LOADx
is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
Rev. E | Page 4 of 27
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
PVIN1, PVIN2, PVINSYS
INBK
SW1
SW2
PGND, AGND
VREG
EN1, EN2, FB1, FB2, SYNC/FREQ
COMP1, COMP2, SLEW, SS,
SEQ, VREF
Operating Junction
Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +18 V
−0.3 V to PVIN1 + 0.3 V
−0.3 V to +40 V
PVIN2 − 40 V to PVIN2 + 0.3 V
−0.3 V to +0.3 V
−0.3 V to lower of PVINSYS +
0.3 V or +6 V
−0.3 V to +6 V
−0.3 V to VREG + 0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
ADP5071
THERMAL RESISTANCE
θ
JA
and Ψ
JT
are based on a 4-layer printed circuit board (PCB)
(two signal and two power planes) with nine thermal vias
connecting the exposed pad to the ground plane as recommended
in the Layout Considerations section. θ
JC
is measured at the top
of the package and is independent of the PCB. The Ψ
JT
value is
more appropriate for calculating junction to case temperature in
the application.
Table 4. Thermal Resistance
Package Type
20-Lead LFCSP
20-Lead TSSOP
θ
JA
60.2
58.5
θ
JC
36.5
35.0
Ψ
JT
0.63
0.60
Unit
°C/W
°C/W
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
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