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(iii) prevention against any malfunction or mishap.
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Rev. 3.00 Jul 08, 2005 page ii of xiv
Main Revisions for this Edition
Item
1.1 Features
Page
1
Revision (See Manual for Details)
Description amended
The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set
computer) microprocessor that is upward-compatible with the SH-
1, SH-2, and SH-2E at the object code level.
2.2.2 Control
Registers
(1) Status Register,
SR
3.1.1 Exception
Handling Types and
Priority
Table 3.1 Exception
Types and Priority
3.1.2 Exception
Handling Operation
(2) Address Error,
RAM Error, Register
Bank Error, Interrupt,
or Instruction
Exception Handling
3.3.1 Address Error 22
Sources
Table 3.5 Bus
Cycles and Address
Errors
3.6.3 Interrupt
Exception Handling
26
18
Description amended
⋅⋅⋅
and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
16
5
Description amended
(32-bit,
00XX)
initial value =0000 0000 0000 0000 00X0 00XX 1111
Note amended
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR,
RTS, RTE,
BF/S, BT/S, BSRF, BRAF
.
Table amended
Bus Cycle
Type
Data
read/write
Bus Master
CPU or
DMAC
Bus Cycle Operation
Double longword data accessed from double
longword boundary
Double longword data accessed from other
than double longword boundary
Address Error
Occurrence
No error (normal)
Address error
Description amended
⋅⋅⋅
and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
Rev. 3.00 Jul 08, 2005 page iii of xiv
Item
6.4.48 RTE
ReTurn from
Exception
System Control
Instruction
6.4.50
SETT
SET T bit
System Control
Instruction
6.4.57 SLEEP
SLEEP
System Control
Instruction
6.5.10 FLOAT
Floating-point
convert from integer
Floating-Point
Instruction
7.1 Overview
Figure 7.1 Overview
of Register Bank
Configuration
7.2.1 Banked Data
7.2.2 Register
Banks
7.2.3 Bank Control
Registers
(2) Bank Number
Register (IBNR) (16
bit, Initial value:
H'0000)
7.3.1 Save to Bank
Page
244
Revision (See Manual for Details)
Description amended
Return from
Exception Handling
Delayed Branch Instruction
248
Description amended
T Bit Setting
257
Description amended
Transition to Power-Down Mode
.
296
Description amended
⋅⋅⋅
When FPSCR.enable.I = 1, and FPSCR.PR = 0, an FPU
exception trap is generated regardless of whether or not an
exception has occurred.⋅⋅⋅
325
Figure amended
(Before) IVO
→
(After) VTO
Figure notes amended
VTO: Interrupt vector table address offset
326
326
327
Description amended
⋅⋅⋅
and the interrupt vector table address offsets (VTO) are banked.
Description amended
⋅⋅⋅
Register banks are stacked in first in last out (FILO) sequence.⋅⋅⋅
Description amended
Bits 3 to 0: BN3 to BN0
⋅⋅⋅
after which the data is retrieved from the register bank. These
bits are read-only and cannot be modified.
328
Description amended
(b) ..., and the interrupt vector table address offset (VTO) are
saved to the bank indicated by the BN, bank i.
Figure 7.2 Bank
Save Operations
Figure 7.3 Bank
Save Timing
328,
329
Figure amended
(Before) IVN
→
(After) VTO
Rev. 3.00 Jul 08, 2005 page v of xiv
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