Operating Temperature Range (Note 4).... –40°C to 85°C
Specified Temperature Range (Note 5) .... –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
1
2
3
4
5
6
7
8
9
23
22 –OUT A
21 V
+
A
20 V
–
19 V
OCMA
18 +OUT A
17 V
–
16 –OUT B
15 V
+
B
14 V
–
13 V
OCMB
12 +OUT B
+IN2 B
+IN1 B
BIAS B
–IN1 B 10
–IN2 B 11
DJC PACKAGE
22-LEAD (6mm
×
3mm) PLASTIC DFN
T
JMAX
= 150°C,
θ
JA
= 46.5°C/W
,
EXPOSED PAD (PIN 23) IS V
–
MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC6605CDJC-14#PBF
LTC6605IDJC-14#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
22-Lead (6mm
×
3mm) Plastic DFN
22-Lead (6mm
×
3mm) Plastic DFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
LTC6605CDJC-14#TRPBF 660514
LTC6605IDJC-14#TRPBF 660514
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
DC ELECTRICAL CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 3V, V
–
= 0V, V
INCM
= V
OCM
= mid-supply, BIAS tied to V
+
, R
L
=
Open, R
BAL
= 10k. The filter is configured for a gain of 1, unless otherwise noted. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as
(V
+OUT
+ V
–OUT
)/2. V
INCM
is defined as (V
INP
+ V
INM
)/2. V
OUTDIFF
is defined as (V
+OUT
– V
–OUT
). V
INDIFF
is defined as (V
INP
– V
INM
).
See Figure 1.
PARAMETER
Differential Offset Voltage (at Op Amp
Inputs) (Note 6)
Differential Offset Voltage Drift (at Op
Amp Inputs)
Input Bias Current (at Op Amp Inputs)
(Note 7)
Input Offset Current
(at Op Amp Inputs) (Note 7)
CONDITIONS
V
S
= 2.7V to 5V
BIAS = V
+
BIAS = Floating
BIAS = V
+
BIAS = Floating
l
l
l
l
l
SYMBOL
V
OS
ΔV
OS
/ΔT
I
B
I
OS
MIN
TYP
±0.25
±1
±1
MAX
±1
UNITS
mV
μV/°C
μV/°C
–60
–30
–25
–12.5
±1
0
0
μA
μA
μA
660514f
2
LTC6605-14
DC ELECTRICAL CHARACTERISTICS
See Figure 1.
The
l
denotes the specifications which apply over the full operating
+
= 3V, V
–
= 0V, V
+
temperature range, otherwise specifications are at T
A
= 25°C. V
INCM
= V
OCM
= mid-supply, BIAS tied to V , R
L
=
Open, R
BAL
= 10k. The filter is configured for a gain of 1, unless otherwise noted. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as
(V
+OUT
+ V
–OUT
)/2. V
INCM
is defined as (V
INP
+ V
INM
)/2. V
OUTDIFF
is defined as (V
+OUT
– V
–OUT
). V
INDIFF
is defined as (V
INP
– V
INM
).
PARAMETER
Input Common Mode Voltage Range
(Note 8)
Common Mode Rejection Ratio
(ΔV
INCM
/ΔV
OS
) (Note 9)
Power Supply Rejection Ratio
(ΔV
S
/ΔV
OS
) (Note 10)
Common Mode Offset Voltage
(V
OUTCM
– V
OCM
)
Output Common Mode Range
(Valid Range for V
OCM
Pin) (Note 8)
Self-Biased Voltage at the V
OCM
Pin
Input Resistance of V
OCM
Pin
Output Voltage Swing, High
(Measured Relative to V
+
)
V
S
= 3V; I
L
= 0mA
V
S
= 3V; I
L
= 5mA
V
S
= 3V; I
L
= 20mA
V
S
= 5V; I
L
= 0mA
V
S
= 5V; I
L
= 5mA
V
S
= 5V; I
L
= 20mA
Output Voltage Swing, Low
(Measured Relative to V
–
)
V
S
= 3V; I
L
= 0mA
V
S
= 3V; I
L
= –5mA
V
S
= 3V; I
L
= –20mA
V
S
= 5V; I
L
= 0mA
V
S
= 5V; I
L
= –5mA
V
S
= 5V; I
L
= –20mA
I
SC
V
S
I
S
Output Short-Circuit Current (Note 3)
Supply Voltage
Supply Current (per Channel)
V
S
= 2.7V to 5V; BIAS = V
+
V
S
= 2.7V to 5V; BIAS = Floating
V
S
= 2.7V to 5V; BIAS = V
–
Referenced to V
–
Referenced to V
–
Referenced to V
–
V
S
= 3V
V
S
= 5V
CONDITIONS
V
S
= 3V
V
S
= 5V
V
S
= 3V;
ΔV
INCM
= 1.5V
V
S
= 5V;
ΔV
INCM
= 2.5V
V
S
= 2.7V to 5V
V
S
= 3V
V
S
= 5V
V
S
= 3V
V
S
= 5V
V
S
= 3V
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
SYMBOL
V
INCM
CMRR
PSRR
V
OSCM
V
OCM
V
MID
R
VOCM
V
OUT
MIN
–0.2
–0.2
46
46
66
TYP
MAX
1.7
4.7
UNITS
V
V
dB
dB
dB
74
74
95
±10
±10
±15
±15
2
4
1.5
18.8
245
285
415
350
390
550
120
135
195
175
200
270
1.525
23.5
450
525
750
625
700
1000
225
250
350
325
360
475
mV
mV
V
V
V
kΩ
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
1.1
1.1
1.475
12.5
±40
±50
2.7
±70
±95
5.25
33.1
16.2
0.35
45
26.5
1.6
0.4
1.5
V
S
1.15
150
400
400
1.25
200
V
mA
mA
mA
V
V
V
V
kΩ
ns
ns
BIAS Pin Range for Shutdown
BIAS Pin Range for Medium Power
BIAS Pin Range for Full Power
R
BIAS
t
ON
t
OFF
BIAS Pin Input Resistance
Turn-On Time
Turn-Off Time
0
1
2.3
1.05
100
BIAS Pin Self-Biased Voltage (Floating) Referenced to V
–
V
S
= 3V, V
BIAS
= V
–
to V
+
V
S
= 3V, V
BIAS
= V
+
to V
–
660514f
3
LTC6605-14
AC ELECTRICAL CHARACTERISTICS
SYMBOL
Gain
PARAMETER
Filter Gain
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 3V, V
–
= 0V, V
INCM
= V
OCM
= mid-supply, V
BIAS
= V
+
, unless
otherwise noted. Filter configured as in Figure 2, unless otherwise noted. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as (V
+OUT
+
V
–OUT
)/2. V
INCM
is defined as (V
+IN
+ V
–IN
)/2. V
OUTDIFF
is defined as (V
+OUT
– V
–OUT
). V
INDIFF
is defined as (V
+IN
+ V
–IN
).
CONDITIONS
ΔV
IN
= ±0.125V, DC
V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
V
INDIFF
= 0.5V
P-P
, f = 28MHz
V
INDIFF
= 0.5V
P-P
, f = 70MHz
ΔV
IN
= ±0.125V, DC
V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
ΔV
IN
= ±0.125V, DC
V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
ΔV
IN
= ±0.125V, DC
V
INDIFF
= 1V
P-P
, f = 7MHz
BIAS = V
+
BIAS = Floating
l
l
l
l
l
l
l
l
l
l
l
l
l
l
MIN
–0.25
–1.25
–2.5
–4.15
–11.65
–28
TYP
±0.05
–0.92
–2.12
–3.75
–11.1
–25.2
0
–43.3
–63.6
–81.2
MAX
0.25
–0.6
–1.75
–3.35
–10.6
–24.3
UNITS
dB
dB
dB
dB
dB
dB
Deg
Deg
Deg
Deg
Phase
Filter Phase
ΔGain
Gain Match (Channel-to-Channel)
–0.175
–0.2
–0.2
–0.25
–0.9
–1.0
–1.1
5.8
±0.04
±0.04
±0.04
±0.05
±0.2
±0.2
±0.2
6
–96
–95
–230
54
0.175
0.2
0.2
0.25
0.9
1.0
1.1
6.25
dB
dB
dB
dB
Deg
Deg
Deg
dB
dB
ppm/°C
ppm/°C
μV
RMS
ΔPhase
Phase Match (Channel-to-Channel)
2V/V Gain
Filter Gain in 2V/V Configuration
Inputs at ±IN1 Pins, ±IN2 Pins Floating
Channel Separation
Filter Cut-Off Frequency Temperature
Coefficient (T = –45°C to 85°C)
Integrated Output Noise
(BW = 10kHz to 28MHz)
Input Referred Noise Density
(f = 1MHz)
f
O
TC
Noise
BIAS = V
+
Figure 4, Gain = 1
Figure 4, Gain = 2
Figure 4, Gain = 3
BIAS = V
+
BIAS = Floating
BIAS = V
+
BIAS = Floating
BIAS = V
+
BIAS = Floating, R
LOAD
= 400Ω
BIAS = V
+
BIAS = Floating, R
LOAD
= 400Ω
13.2
6.6
4.4
2.1
2.6
3
2.1
–81
–69
–93
–76
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
dBc
dBc
dBc
dBc
e
n
i
n
HD2
HD3
Voltage Noise Density Referred to
Op Amp Inputs (f = 1MHz)
Current Noise Density Referred to
Op Amp Inputs (f = 1MHz)
2nd Harmonic Distortion
f
IN
= 7MHz; V
IN
= 2V
P-P
Single-Ended
3rd Harmonic Distortion
f
IN
= 7MHz; V
IN
= 2V
P-P
Single-Ended
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All pins are protected by steering diodes to either supply. If any
pin is driven beyond the LTC6605-14’s supply voltage, the excess input
current (current in excess of what it takes to drive that pin to the supply
rail) should be limited to less than 10mA.
Note 3:
A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.
Note 4:
Both the LTC6605C and the LTC6605I are guaranteed functional
over the operating temperature range –40°C to 85°C.
Note 5:
The LTC6605C is guaranteed to meet specified performance
from 0°C to 70°C. The LTC6605C is designed, characterized and
expected to meet specified performance from –40°C to 85°C, but is
not tested or QA sampled at these temperatures. The LTC6605I is
guaranteed to meet specified performance from –40°C to 85°C.
Note 6:
Output referred voltage offset is a function of gain. To determine
output referred voltage offset, or output voltage offset drift, multiply V
OS
by the noise gain (1 + GAIN). See Figure 3.
Note 7:
Input bias current is defined as the average of the currents
flowing into the noninverting and inverting inputs of the internal amplifier
and is calculated from measurements made at the pins of the IC. Input
offset current is defined as the difference of the currents flowing into
the noninverting and inverting inputs of the internal amplifier and is
calculated from measurements made at the pins of the IC.
660514f
4
LTC6605-14
ELECTRICAL CHARACTERISTICS
Note 8:
See the Applications Information section for a detailed
discussion of input and output common mode range. Input common
mode range is tested by measuring the differential DC gain with V
INCM
= mid-supply, and again with V
INCM
at the input common mode range
limits listed in the Electrical Characteristics table, with ΔV
IN
= ±0.25,
verifying that the differential gain has not deviated from the mid-supply
common mode input case by more than 0.5%, and that the common
mode offset (V
OSCM
) has not deviated from the mid-supply common
mode offset by more than ±10mV.
Output common mode range is tested by measuring the differential DC
gain with V
OCM
= mid-supply, and again with voltage set on the V
OCM
pin
at the output common range limits listed in the Electrical Characteristics
table, verifying that the differential gain has not deviated from the
mid-supply common mode input case by more than 0.5%, and that the
common mode offset (V
OSCM
) has not deviated by more than ±10mV
from the mid-supply case.
Note 9:
CMRR is defined as the ratio of the change in the input common
mode voltage at the internal amplifier inputs to the change in differential
input referred voltage offset (V
OS
).
Note 10:
Power supply rejection ratio (PSRR) is defined as the ratio of
the change in supply voltage to the change in differential input referred
京公网安备 11010802033920号
EEWORLD
