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HB54A5128FN-A75B

Description
512MB Unbuffered DDR SDRAM DIMM
Categorystorage    storage   
File Size181KB,17 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
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HB54A5128FN-A75B Overview

512MB Unbuffered DDR SDRAM DIMM

HB54A5128FN-A75B Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerELPIDA
Parts packaging codeDIMM
package instructionDIMM, DIMM184
Contacts184
Reach Compliance Codeunknow
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)143 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N184
memory density4294967296 bi
Memory IC TypeDDR DRAM MODULE
memory width64
Humidity sensitivity level1
Number of functions1
Number of ports1
Number of terminals184
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature55 °C
Minimum operating temperature
organize64MX64
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM184
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)225
power supply2.5 V
Certification statusNot Qualified
refresh cycle8192
self refreshYES
Maximum slew rate2.2 mA
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
DATA SHEET
512MB Unbuffered DDR SDRAM DIMM
HB54A5128FN-A75B/B75B/10B
(64M words
×
64 bits, 2 Banks)
HB54A5129FN-A75B/B75B/10B
(64M words
×
72 bits, 2 Banks)
Description
The HB54A5128FN, HB54A5129FN are Double Data
Rate (DDR) SDRAM Module, mounted 256M bits DDR
SDRAM (HM5425801BTT) sealed in TSOP package,
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD).
The HB54A5128FN is
organized as 32M
×
64
×
2 banks mounted 16 pieces
of 256M bits DDR SDRAM. The HB54A5129FN is
organized as 32M
×
72
×
2 banks mounted 18 pieces
of 256M bits DDR SDRAM. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
184-pin socket type package (dual lead out).
Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the module board.
Features
184-pin socket type package (dual lead out)
Outline: 133.35mm (Length)
×
31.75mm (Height)
×
4.00mm (Thickness)
Lead pitch: 1.27mm
2.5V power supply (VCC/VCCQ)
SSTL-2 interface for all inputs and outputs
Clock frequency: 143MHz/133MHz/125MHz (max.)
Data inputs, outputs and DM are synchronized with
DQS
4 banks can operate simultaneously and
independently (Component)
Burst read/write operation
Programmable burst length: 2, 4, 8
Burst read stop capability
Programmable burst sequence
Sequential
Interleave
Start addressing capability
Even and Odd
Programmable /CAS latency (CL): 2, 2.5
8192 refresh cycles: 7.8µs (8192/64ms)
2 variations of refresh
Auto refresh
Self refresh
EO
Document No. E0087H40 (Ver. 4.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2001-2002
Hitachi,
Ltd. 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
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Pr
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HB54A5128FN-A75B Related Products

HB54A5128FN-A75B HB54A5129FN-B75B HB54A5129FN-10B HB54A5128FN-B75B HB54A5128FN-10B
Description 512MB Unbuffered DDR SDRAM DIMM 512MB Unbuffered DDR SDRAM DIMM 512MB Unbuffered DDR SDRAM DIMM 512MB Unbuffered DDR SDRAM DIMM 512MB Unbuffered DDR SDRAM DIMM
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible
Maker ELPIDA ELPIDA ELPIDA ELPIDA ELPIDA
Parts packaging code DIMM DIMM DIMM DIMM DIMM
package instruction DIMM, DIMM184 DIMM, DIMM184 DIMM, DIMM184 DIMM, DIMM184 DIMM, DIMM184
Contacts 184 184 184 184 184
Reach Compliance Code unknow unknown unknow unknow unknow
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99
access mode DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST
Maximum access time 0.75 ns 0.75 ns 0.8 ns 0.75 ns 0.8 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) 143 MHz 133 MHz 125 MHz 133 MHz 125 MHz
I/O type COMMON COMMON COMMON COMMON COMMON
JESD-30 code R-XDMA-N184 R-XDMA-N184 R-XDMA-N184 R-XDMA-N184 R-XDMA-N184
memory density 4294967296 bi 4831838208 bit 4831838208 bi 4294967296 bi 4294967296 bi
Memory IC Type DDR DRAM MODULE DDR DRAM MODULE DDR DRAM MODULE DDR DRAM MODULE DDR DRAM MODULE
memory width 64 72 72 64 64
Humidity sensitivity level 1 1 1 1 1
Number of functions 1 1 1 1 1
Number of ports 1 1 1 1 1
Number of terminals 184 184 184 184 184
word count 67108864 words 67108864 words 67108864 words 67108864 words 67108864 words
character code 64000000 64000000 64000000 64000000 64000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 55 °C 55 °C 55 °C 55 °C 55 °C
organize 64MX64 64MX72 64MX72 64MX64 64MX64
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code DIMM DIMM DIMM DIMM DIMM
Encapsulate equivalent code DIMM184 DIMM184 DIMM184 DIMM184 DIMM184
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius) 225 225 225 225 225
power supply 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
refresh cycle 8192 8192 8192 8192 8192
self refresh YES YES YES YES YES
Maximum slew rate 2.2 mA 2.34 mA 2.205 mA 2.08 mA 1.96 mA
Maximum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
Minimum supply voltage (Vsup) 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
surface mount NO NO NO NO NO
technology CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD
Terminal pitch 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED

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