ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ V
DD1
≤ 5.5 V, V
SEL
= V
ISO
; all voltages are relative to their respective ground. All minimum/maximum specifications apply over the
entire recommended operating range, unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= 5.0 V, V
SEL
= V
ISO
= 5.0 V.
Table 1.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
iCoupler
DATA CHANNELS
DC to 2 Mbps Data Rate
1
Maximum Output Supply Current
2
Efficiency at Maximum Output Supply
Current
3
I
DD1
Supply Current, No V
ISO
Load
25 Mbps Data Rate (CRWZ Grade Only)
I
DD1
Supply Current, No V
ISO
Load
ADuM5401
ADuM5402
ADuM5403
ADuM5404
Available V
ISO
Supply Current
4
ADuM5401
ADuM5402
ADuM5403
ADuM5404
I
DD1
Supply Current, Full V
ISO
Load
I/O Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Symbol
V
ISO
V
ISO(LINE)
V
ISO(LOAD)
V
ISO(RIP)
V
ISO(N)
f
OSC
f
PWM
Min
4.7
Typ
5.0
1
1
75
200
180
625
Max
5.4
5
Unit
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
Test Conditions/Comments
I
ISO
= 0 mA
I
ISO
= 50 mA, V
DD1
= 4.5 V to 5.5 V
I
ISO
= 10 mA to 90 mA
20 MHz bandwidth, C
BO
= 0.1 μF║10 μF,
I
ISO
= 90 mA
20 MHz bandwidth, C
BO
= 0.1 μF║10 μF,
I
ISO
= 90 mA
I
ISO(MAX)
100
34
mA
%
30
mA
f ≤ 1 MHz, V
ISO
> 4.5 V
I
ISO
= I
ISO(2,MAX)
, f ≤ 1 MHz
I
ISO
= 0 mA, f ≤ 1 MHz
I
DD1(Q)
I
DD1(D)
19
68
71
75
78
I
ISO(LOAD)
87
85
83
81
290
+0.01
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
V
V
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 0 pF, f = 0 MHz, V
DD
= 5 V, I
ISO
= 100 mA
I
DD1(MAX)
I
IA
, I
IB
, I
IC
, I
ID
V
IH
V
IL
−20
0.7 × V
ISO
,
0.7 × V
IDD1
+20
0.3 × V
ISO
,
0.3 ×
V
IDD1
V
DD1
− 0.3,
V
ISO
− 0.3
V
DD1
− 0.5,
V
ISO
− 0.3
5.0
4.8
0.0
0.0
0.1
0.4
Logic High Output Voltages
V
OAH
, V
OBH
,
V
OCH
, V
ODH
V
V
V
V
I
Ox
= −20 μA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 μA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
Logic Low Output Voltages
V
OAL
, V
OBL
,
V
OCL
, V
ODL
AC SPECIFICATIONS
ADuM5401ARWZ/ADuM5402ARWZ/
ADuM5403ARWZ/ADuM5404ARWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Propagation Delay Skew
Channel-to-Channel Matching
PW
1
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
/t
PSKOD
55
1000
100
40
50
50
ns
Mbps
ns
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Rev. 0 | Page 3 of 24
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Parameter
ADuM5401CRWZ/ADuM5402CRWZ/
ADuM5403CRWZ/ADuM5404CRWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
Refresh Rate
1
2
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
PW
25
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
2.5
35
35
1.0
45
5
40
60
6
15
6
15
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD
or V
ISO
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V = 1000 V,
transient magnitude = 800 V
25
25
The contributions of supply current values for all four channels are combined at identical data rates.
The V
ISO
supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the V
ISO
power budget.
3
The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4
This current is available for driving external loads at the V
ISO
pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
Rev. 0 | Page 4 of 24
ADuM5401/ADuM5402/ADuM5403/ADuM5404
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V ≤ V
DD1
≤ 3.6 V, V
SEL
= GND
ISO
; all voltages are relative to their respective ground. All minimum/maximum specifications apply over
the entire recommended operating range, unless otherwise noted. All typical specifications are at T
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