ADVANCED INFORMATION
MX69LW1621/1641T/B
16M-BIT [X16] FLASH AND 2M-BIT/4M-BIT [X16] SRAM
MIXED MULTI CHIP PACKAGE MEMORY
FEATURES
• Supply voltage range: 2.7V to 3.6V
• Fast access time: Flash memory:70/90ns
SRAM memory:70/85ns
• Operation temperature range: -40 ~ 85°
C
• 100,000 minimum erase/program cycles
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Status Register feature for detection of program or
erase cycle completion
• Read While Write Operation between Bank I, Bank II
• Software command control
• Selective Block Lock
FLASH
Word mode only
15mA maximum active current
0.1uA typical standby current
Program Time: 4ms typical /each blocks
Auto program for Bank I (2Mb)
- Word Programming (1 word)
- Page Programming (128 word)
• Auto program for Bank II (14Mb)
- Page programming (128 word)
• Auto erase operation
- Automatically erases any combination of the blocks
- Fast erase time: 40ms typical for single block erase
•
•
•
•
•
SRAM
•
•
•
•
•
•
MX69LW1621T/B: 128K wordx16 Bit
MX69LW1641T/B: 256K wordx16 Bit
70mA maximum active current
1uA typical standby current
Data retention supply voltage: 2.0V~3.6V
Byte data control : LBs(Q0 to Q7) and UBs(Q8 to Q15)
GENERAL DESCRIPTION
The MXIC's mixed multi chip memory combines Flash
and SRAM into a single package. The mixed multi chip
memory operates 2.7 to 3.6V power supply to allow for
simple in-system operation.
The Flash memory of mixed multi chip memory manu-
factured with MXIC's advanced nonvolatile memory tech-
nology, the flash memory of mixed multi chip memory
provide simultaneous operation which can read data while
program/erase, the data is divided into two banks of
Bank I and BankII. The device offers access times of
70ns/90ns, and a low 0.1uA typical standby current.
The 2M-bit SRAM of MX69LW1621T/B is organized as
128K-word by 16-bit. The 4M-bit SRAM of
MX69LW1641T/B is organized as 256K-word by 16-bit.
The advanced CMOS technology and circuit techniques
provide both high speed and low power features of with
a typical CMOS standby current of 1uA and maximum
access time of 70ns/85ns in 3V operation.
The mixed multi chip memory is available in 11mm x
8mm FBGA Package to suit a variety of design applica-
tions.
P/N:PM0925
REV. 0.1, MAY 02, 2003
1
MX69LW1621/1641T/B
PIN ASSIGNMENT
1.66-ball CSP for MX69LW1621/1641T/B (Top View Balls Down, Ball Pitch=0.8mm)
A
B
C
D
E
F
G
H
NC
NC
NC
A11
A15
A14
A13
A12
GNDf
NC
NC
NC
A16
A8
A10
A9
Q15
WEs
Q14
Q7
WEf
NC
Q13
Q6
Q4
Q5
GNDs
RESET
Q12
CE2s
VCCs
VCCf
WP
NC
A19
Q11
Q10
Q2
Q3
8.0 mm
LBs
UBs
OEs
Q9
Q8
Q0
Q1
A18
A17
A7
A6
A3
A2
A1
CE1s
NC
NC
NC
A5
A4
A0
CEf
GNDf
OEf
NC
NC
NC
1
2
3
4
5
6
7
11.0 mm
8
9
10
11
12
Notes:
1.To maintain compatibility with all JEDEC Variation B options for this ball location C6, this C6 land pad should be
connected directly to the land pad for ball G4 (A17).
PIN DESCRIPTION
SYMBOL
A0 to A16
A0 to A17
A17 to A19
A18 to A19
Q0 to Q15
CEf
CE1s
CE2s
OEf
OEs
PIN NAME
Address Inputs (Common) for
MX69LW1621T/B
Address Inputs (Common) for
MX69LW1641T/B
Address Input (Flash) for
MX69LW1621T/B
Address Input (Flash) for
MX69LW1641T/B
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Flash)
Output Enable (SRAM)
SYMBOL
WEf
WEs
UBs
LBs
RESET
WP
N.C.
GND
Vccf
Vccs
PIN NAME
Write Enable (Flash)
Write Enable (SRAM)
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
Hardware Reset Pin/Sector
Protection Unlock (Flash)
Write Protect
No Connection
Ground Pin (Common)
Power Supply (Flash)
Power Supply (SRAM)
P/N:PM0925
REV. 0.1, MAY 02, 2003
3