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Spartan-3 FPGA Family
Data Sheet
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DS099 June 25, 2008
Product Specification
This document includes all four modules of the Spartan
®
-3 FPGA data sheet.
Module 1:
Spartan-3 FPGA Family: Introduction
and Ordering Information
DS099-1 (v2.4) June 25, 2008
•
•
•
•
•
•
Introduction
Features
Architectural Overview
Array Sizes and Resources
User I/O Chart
Ordering Information
Module 3:
Spartan-3 FPGA Family: DC and
Switching Characteristics
DS099-3 (v2.4) June 25, 2008
•
DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- I/O Timing
- Internal Logic Timing
- DCM Timing
- Configuration and JTAG Timing
•
Module 2:
Spartan-3 FPGA Family: Functional
Description
DS099-2 (v2.4) June 25, 2008
•
Input/Output Blocks (IOBs)
- IOB Overview
- SelectIO™ Interface I/O Standards
Configurable Logic Blocks (CLBs)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Module 4:
Spartan-3 FPGA Family: Pinout
Descriptions
DS099-4 (v2.4) June 25, 2008
•
•
•
Pin Descriptions
- Pin Behavior During Configuration
Package Overview
Pinout Tables
- Footprints
•
•
•
•
•
•
IMPORTANT NOTE:
Each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation
in this volume.
© 2003-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099 June 25, 2008
Product Specification
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DS099 June 25, 2008
Product Specification
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10
Spartan-3 FPGA Family:
Introduction and Ordering
Information
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DS099-1 (v2.4) June 25, 2008
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Product Specification
Introduction
The Spartan
®
-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
five million system gates, as shown in
Table 1.
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from the Virtex
®
-II platform technol-
ogy. These Spartan-3 FPGA enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
The Spartan-3 FPGAs are the first platform among several
within the
Spartan-3 Generation FPGAs.
Features
•
Low-cost, high-performance logic solution for high-volume,
consumer-oriented applications
-
Densities up to 74,880 logic cells
SelectIO™ interface signaling
-
Up to 633 I/O pins
-
622 Mb/s data transfer rate per I/O
-
18 single-ended signal standards
-
8 differential I/O standards including LVDS, RSDS
-
Termination by Digitally Controlled Impedance
-
Signal swing ranging from 1.14V to 3.465V
-
Double Data Rate (DDR) support
-
DDR, DDR2 SDRAM support
up to 333 Mbps
Logic resources
-
Abundant logic cells with shift register capability
-
Wide, fast multiplexers
-
Fast look-ahead carry logic
-
Dedicated 18 x 18 multipliers
-
JTAG logic compatible with IEEE 1149.1/1532
SelectRAM™ hierarchical memory
-
Up to 1,872 Kbits of total block RAM
-
Up to 520 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
-
Clock skew elimination
-
Frequency synthesis
-
High resolution phase shifting
Eight global clock lines and abundant routing
•
•
•
•
•
•
•
•
Fully supported by
Xilinx ISE
®
and
WebPACK™
software development systems
MicroBlaze™
and
PicoBlaze™
processor,
PCI
®
,
PCI
Express
®
PIPE Endpoint,
and other
IP cores
Pb-free packaging options
Automotive
Spartan-3 XA Family
variant
•
Table 1:
Summary of Spartan-3 FPGA Attributes
Equivalent
Logic
Cells
1
CLB Array
(One CLB = Four Slices)
Rows
Columns
Total
CLBs
Device
System
Gates
Distributed
RAM Bits
(K=1024)
Block RAM
Bits
(K=1024)
Dedicated
Multipliers
DCMs
Maximum
User I/O
Maximum
Differential
I/O Pairs
XC3S50
2
XC3S200
2
XC3S400
2
XC3S1000
2
XC3S1500
XC3S2000
XC3S4000
XC3S5000
50K
200K
400K
1M
1.5M
2M
4M
5M
1,728
4,320
8,064
17,280
29,952
46,080
62,208
74,880
16
24
32
48
64
80
96
104
12
20
28
40
52
64
72
80
192
480
896
1,920
3,328
5,120
6,912
8,320
12K
30K
56K
120K
208K
320K
432K
520K
72K
216K
288K
432K
576K
720K
1,728K
1,872K
4
12
16
24
32
40
96
104
2
4
4
4
4
4
4
4
124
173
264
391
487
565
633
633
56
76
116
175
221
270
300
300
Notes:
1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness.
2. These devices are available in Xilinx Automotive versions as described in
DS314:
Spartan-3 Automotive XA FPGA Family.
© 2003-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-1 (v2.4) June 25, 2008
Product Specification
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3
Spartan-3 FPGA Family: Introduction and Ordering Information
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Architectural Overview
The Spartan-3 family architecture consists of five funda-
mental programmable functional elements:
•
Configurable Logic Blocks (CLBs) contain RAM-based
Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of
logical functions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Twenty-six different signal standards,
including eight high-performance differential standards,
are available as shown in
Table 2.
Double Data-Rate
(DDR) registers are included. The Digitally Controlled
Impedance (DCI) feature provides automatic on-chip
terminations, simplifying board designs.
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
Multiplier blocks accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase shifting clock
signals.
•
These elements are organized as shown in
Figure 1.
A ring
of IOBs surrounds a regular array of CLBs. The XC3S50
has a single column of block RAM embedded in the array.
Those devices ranging from the XC3S200 to the XC3S2000
have two columns of block RAM. The XC3S4000 and
XC3S5000 devices have four RAM columns. Each column
is made up of several 18-Kbit RAM blocks; each block is
associated with a dedicated multiplier. The DCMs are posi-
tioned at the ends of the outer block RAM columns.
The Spartan-3 family features a rich network of traces and
switches that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple con-
nections to the routing.
•
•
DS099-1_01_032703
Notes:
1. The two additional block RAM columns of the XC3S4000 and XC3S5000
devices are shown with dashed lines. The XC3S50 has only the block RAM
column on the far left.
Figure 1:
Spartan-3 Family Architecture
4
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DS099-1 (v2.4) June 25, 2008
Product Specification
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Spartan-3 FPGA Family: Introduction and Ordering Information
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust, reprogrammable, static CMOS configura-
tion latches (CCLs) that collectively control all functional
elements and routing resources. Before powering on the
FPGA, configuration data is stored externally in a PROM or
some other nonvolatile medium either on or off the board.
After applying power, the configuration data is written to the
FPGA using any of five different modes: Master Parallel,
Slave Parallel, Master Serial, Slave Serial, and Boundary
Scan (JTAG). The Master and Slave Parallel modes use an
8-bit wide SelectMAP port.
Standard
Category
Single-Ended
GTL
Gunning Transceiver Logic
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18 sin-
gle-ended standards and 8 differential standards as listed in
Table 2.
Many standards support the DCI feature, which
uses integrated terminations to eliminate unwanted signal
reflections..
V
CCO
(V)
N/A
Table 2:
Signal Standards Supported by the Spartan-3 Family
Description
Class
Terminated
Plus
HSTL
High-Speed Transceiver Logic
1.5
I
III
1.8
I
II
III
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
LVTTL
PCI
SSTL
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
3.3
3.0
1.8
N/A
N/A
N/A
N/A
N/A
N/A
33 MHz
(1)
N/A (±6.7 mA)
N/A (±13.4 mA)
2.5
I
II
Differential
LDT
(ULVDS)
LVDS
Lightning Data Transport (HyperTransport™)
Logic
Low-Voltage Differential Signaling
2.5
N/A
Standard
Bus
Extended Mode
LVPECL
RSDS
HSTL
SSTL
Low-Voltage Positive Emitter-Coupled Logic
Reduced-Swing Differential Signaling
Differential High-Speed Transceiver Logic
Differential Stub Series Terminated Logic
2.5
2.5
1.8
2.5
N/A
N/A
II
II
LDT_25
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_SSTL2_II
No
Yes
No
Yes
No
No
Yes
Yes
Symbol
(IOSTANDARD)
GTL
GTLP
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
PCI33_3
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
DCI
Option
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
Yes
Notes:
1. 66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.
DS099-1 (v2.4) June 25, 2008
Product Specification
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