XC2S50-6CSG144I datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> XC2S50-6CSG144I

XC2S50-6CSG144I: DescriptionFPGA, 384 CLBS, 50000 GATES, 263 MHz, PQFP144; Categorysemiconductor Programmable logic devices; File Size76KB，6 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

Download Datasheet Parametric View All

XC2S50-6CSG144I Overview

FPGA, 384 CLBS, 50000 GATES, 263 MHz, PQFP144

XC2S50-6CSG144I Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	2.62 V
Minimum supply/operating voltage	2.38 V
Rated supply voltage	2.5 V
Processing package description	PLASTIC, TQFP-144
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	MATTE TIN
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	OTHER
organize	384 CLBS, 50000 GATES
Maximum FCLK clock frequency	263 MHz
Number of configurable logic modules	384
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	50000
The maximum delay of a CLB module	0.6000 ns

Preview

Download Datasheet

View All

— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —

Spartan-IIE 1.8V FPGA

Automotive XA Product Family:

Introduction and Ordering

DS106-1 (v2.0) August 9, 2013

Product Specification

•

Guaranteed to meet full electrical specifications over

= –40°C to +125°C

Second generation ASIC replacement technology

- Densities as high as 6,912 logic cells with up to

300,000 system gates

- Very low cost

System-level features

- SelectRAM+™ hierarchical memory:

16 bits/LUT distributed RAM

Configurable 4K-bit true dual-port block RAM

Fast interfaces to external RAM

- Dedicated carry logic for high-speed arithmetic

- Efficient multiplier support

- Cascade chain for wide-input functions

- Abundant registers/latches with enable, set, reset

- Four dedicated DLLs for advanced clock control

Eliminate clock distribution delay

Multiply, divide, or phase shift

- Four primary low-skew global clock distribution nets

- IEEE 1149.1 compatible boundary scan logic

Versatile I/O and packaging

- Low-cost packages available in all densities

- 19 high-performance interface standards

LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL

LVDS and LVPECL differential I/O

- Up to 120 differential I/O pairs that can be input,

output, or bidirectional

Fully supported by powerful Xilinx ISE development

system

- Fully automatic mapping, placement, and routing

- Integrated with design entry and verification tools

- Extensive IP library including DSP functions

Introduction

The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Pro-

grammable Gate Array family is specifically designed to

meet the needs of high-volume, cost-sensitive automotive

electronic applications. The family gives users high perfor-

mance, abundant logic resources, and a rich feature set, all

at an exceptionally low price. The five-member family offers

densities ranging from 50,000 to 300,000 system gates, as

shown in

Table 1.

System performance is supported beyond

200 MHz.

Spartan-IIE devices deliver more gates, I/Os, and features

per dollar than other FPGAs by combining advanced pro-

cess technology with a streamlined architecture based on

the proven Virtex™-E platform. Features include block RAM

(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable

I/O standards, and four DLLs (Delay-Locked Loops). Fast,

predictable interconnect means that successive design iter-

ations continue to meet timing requirements.

XA devices are available in both the extended-temperature

Q-grade (-40

C to +125

C) and industrial I-grade (-40

C to

+100

C) and are qualified to the industry-recognized

AEC-Q100 standard.

The XA Spartan-IIE family is a superior alternative to

mask-programmed ASICs. The FPGA avoids the initial cost,

lengthy development cycles, and inherent risk of conven-

tional ASICs. Also, FPGA programmability permits design

upgrades in the field with no hardware replacement neces-

sary (impossible with ASICs).

•

Features

•

AEC-Q100 device qualification and full PPAP support

available in both extended temperature Q-grade and

I-grade

Table 1:

XA Spartan-IIE FPGA Family Members

Logic

Cells

1,728

2,700

3,888

5,292

6,912

Typical

System Gate Range

(Logic and RAM)

23,000 - 50,000

37,000 - 100,000

52,000 - 150,000

71,000 - 200,000

93,000 - 300,000

CLB

Array

(R x C)

16 x 24

20 x 30

24 x 36

28 x 42

32 x 48

Total

CLBs

384

600

864

1,176

1,536

Maximum

Available

User I/O

(1)

102

182

Maximum

Differential

I/O Pairs

114

120

Distributed

RAM Bits

24,576

38,400

55,296

75,264

98,304

Block

RAM Bits

32K

40K

48K

56K

64K

Device

XA2S50E

XA2S100E

XA2S150E

XA2S200E

XA2S300E

Notes:

1. User I/O counts include the four global clock/user input pins. See details in

Table 3, page 5

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS106-1 (v2.0) August 9, 2013

Product Specification

www.xilinx.com

Recommended Resources

desk lamp remote control circuit

SG3524 wiring

Light controlled delay circuit (5)

UM3758 (universal) infrared or ultrasonic remote control transceiver circuit - transmitter circuit

OPC circuit

Photometric circuit using pbs, pbse

Supercapacitors, the best solution for backup power?: A supercapacitor is an electrochemical capacitor that has the ability to store more energy than a conventional capacitor. Supercapacitors can charge and deliver energy faster than batteries. The incre...; qwqwqw2088 Analogue and Mixed Signal

MIPS register conventions: MIPS Register Convention Author: Chen Huailin Translation Source: Embedded Technology Network Hits: 601 Updated: 2007-1-26 Register Convention For development on a CPU, it is very important to master ...; liukaiyue Embedded System

2440 Buffer_preview_info_update problem: temp = (s2440CAM->rCIPRSTATUS>>26)&3; temp = (temp + 2) % 4; RETAILMSG(MSG_EN_2,(_T("preview index = %d, size %d"), temp, image_size )); switch (temp) { case 0: buffer_rgb = s2440CAM->rCIPRCLRSA1; bre...; LIYAN Embedded System

The value of Memory in stm8l during STVD soft simulation is all 0xFF: I am debugging the ST built-in routine.Why are all the memory values 0xFF? How to solve it?Also looking for stm8l1526 evaluation board...; cxsusan1010 stm32/stm8

Let's learn about CC3200 Wi-Fi MCU together: [i=s]This post was last edited by gsjzbj on 2014-12-23 18:47[/i] CC3200 is the latest Wi-Fi MCU launched by TI's wireless connection SimpleLink Wi-Fi and Internet of Things (IoT) solution. It is the i...; gsjzbj Wireless Connectivity

AVX's capacitor problem...: It’s really annoying. I need to find some capacitors. I’ll buy them in Huaqiangbei, but there are many fake ones. I’ll find an agent, they won’t deal with small companies... Is there any solution?...; samhuang8204 Talking about work

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components