74LS112 datasheet, PDF - EEWORLD Datasheet

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74LS112: DescriptionLS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16; Categorysemiconductor logic; File Size46KB，5 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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74LS112 Overview

LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16

74LS112 Parametric

Parameter Name	Attribute value
Number of functions	2
Number of terminals	16
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.25 V
Minimum supply/operating voltage	4.75 V
Rated supply voltage	5 V
Processing package description	0.300 INCH, PLASTIC, MS-001, DIP-16
state	ACTIVE
Craftsmanship	TTL
packaging shape	RECTANGULAR
Package Size	IN-LINE
Terminal form	THROUGH-HOLE
Terminal spacing	2.54 mm
terminal coating	TIN LEAD
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
series	LS
Logic IC type	J-K FLIP-FLOP
Number of digits	2
Output polarity	COMPLEMENTARY
propagation delay TPD	28 ns
Trigger type	NEGATIVE EDGE
Max-Min frequency	25 MHz

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DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary

Outputs

August 1986

Revised March 2000

DM74LS112A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

with Preset, Clear, and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop on the falling edge of

the clock pulse. The clock triggering occurs at a voltage

level and is not directly related to the transition time of the

falling edge of the clock pulse. Data on the J and K inputs

may be changed while the clock is HIGH or LOW without

affecting the outputs as long as the setup and hold times

are not violated. A low logic level on the preset or clear

inputs will set or reset the outputs regardless of the logic

levels of the other inputs.

Ordering Code:

Order Number

DM74KS112AM

DM74LS112AN

Package Number

M16A

N16E

Package Description

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

CLR CLK

↓

H (Note 1)

Toggle

Outputs

H (Note 1)

HIGH Logic Level

LOW Logic Level

Either LOW or HIGH Logic Level

↓ =

Negative Going Edge of Pulse

The output logic level before the indicated input conditions were

established.

Toggle

Each output changes to the complement of its previous level on

each falling edge of the clock pulse.

Note 1:

This configuration is nonstable; that is, it will not persist when

preset and/or clear inputs return to their inactive (HIGH) level.

DS006382

www.fairchildsemi.com

74LS112 Related Products

	74LS112	DM74KS112AM	DM74LS112AN	DM74LS112A
Description	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
Number of functions	2	2	2	2
Number of terminals	16	16	16	16
Maximum operating temperature	70 Cel	70 °C	70 °C	70 Cel
Terminal form	THROUGH-HOLE	GULL WING	THROUGH-HOLE	THROUGH-HOLE
Terminal location	DUAL	DUAL	DUAL	DUAL
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
series	LS	LS	LS	LS
Number of digits	2	2	2	2
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE

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