DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary
Outputs
August 1986
Revised March 2000
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Ordering Code:
Order Number
DM74KS112AM
DM74LS112AN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
PR
L
H
L
H
H
H
H
H
CLR CLK
H
L
L
H
H
H
H
H
X
X
X
↓
↓
↓
↓
H
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Q
0
Q
H
L
H (Note 1)
Q
0
H
L
Toggle
Q
0
Outputs
Q
L
H
H (Note 1)
Q
0
L
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
↓ =
Negative Going Edge of Pulse
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
Note 1:
This configuration is nonstable; that is, it will not persist when
preset and/or clear inputs return to their inactive (HIGH) level.
© 2000 Fairchild Semiconductor Corporation
DS006382
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DM74LS112A
Absolute Maximum Ratings
(Note 2)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 2:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
f
CLK
t
W
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 3)
Clock Frequency (Note 5)
Pulse Width
(Note 3)
t
W
Pulse Width
(Note 5)
t
SU
t
SU
t
H
t
H
T
A
Clock HIGH
Preset LOW
Clear LOW
Clock HIGH
Preset LOW
Clear LOW
Setup Time (Note 3)(Note 4)
Setup Time (Note 4)(Note 5)
Hold Time (Note 3)(Note 4)
Hold Time (Note 4)(Note 5)
Free Air Operating Temperature
0
0
20
25
25
25
30
30
20↓
25↓
0↓
5↓
0
70
ns
ns
ns
ns
°C
ns
ns
Parameter
Min
4.75
2
0.8
−0.4
8
30
25
Nom
5
Max
5.25
Units
V
V
V
mA
mA
MHz
MHz
Note 3:
C
L
=
15 pF, R
L
=
2 kΩ, T
A
=
25°C and V
CC
=
5V.
Note 4:
The symbol (↓) indicates the falling edge of the clock pulse is used for reference.
Note 5:
C
L
=
50 pF, R
L
=
2 kΩ, T
A
=
25°C and V
CC
=
5V.
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2
DM74LS112A
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
I
Input Current @ Max
Input Voltage
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max, V
IH
=
Min
I
OL
=
4 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
J, K
Clear
Preset
Clock
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
J, K
Clear
Preset
Clock
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.4V
J, K
Clear
Preset
Clock
I
OS
I
CC
Short Circuit Output Current
Supply Current
V
CC
=
Max (Note 7)
V
CC
=
Max (Note 8)
−20
4
2.7
3.4
0.35
0.25
0.5
0.4
0.1
0.3
0.3
0.4
20
60
60
80
−0.4
−0.8
−0.8
−0.8
−100
6
mA
mA
mA
µA
mA
Min
Typ
(Note 6)
Max
−1.5
Units
V
V
V
Note 6:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 7:
Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V
O
=
2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 8:
With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
From (Input)
Symbol
Parameter
To (Output)
C
L
=
15 pF
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Preset to Q
30
20
Max
R
L
=
2 kΩ
C
L
=
50 pF
Min
25
24
Max
MHz
ns
Units
Preset to Q
20
28
ns
Clear to Q
Clear to Q
20
20
24
28
ns
ns
Clock to Q or Q
20
24
ns
Clock to Q or Q
20
28
ns
3
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DM74LS112A
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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4
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary
Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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