• Available in Lead-Free 36-lead (400-mil) Molded SOJ
V36 and 44-pin TSOP II ZS44 packages
Functional Description
[1]
The CY7C1049DV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049DV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
GND
I/O
2
I/O3
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
GND
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
TSOP II
Top View
NC
NC
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
I/O
0
INPUT
BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512K x 8
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Selection Guide
Maximum Access Time
Maximum Operating Current
-8
8
90
100
10
-10
10
80
90
10
-12
12
75
85
10
Unit
ns
mA
mA
Commercial
Industrial
Maximum CMOS Standby Current Commercial/Industrial
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05475 Rev. *B
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
NC
NC
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600
Revised July 29 2005
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
CY7C1049DV33
DC Input Voltage
[2]
................................ –0.3V to V
CC
+ 0.3V
Current into Outputs (LOW)......................................... 20 mA
Latch-up Current...................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
.... –0.3V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................–0.3V to V
CC
+ 0.3V
Electrical Characteristics
Over the Operating Range
-8
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Test Conditions
Min.
2.4
0.4
2.0
–0.3
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Com’l
Ind’l
Com’l/Ind’l
–1
–1
V
CC
+ 0.3
0.8
+1
+1
90
100
20
2.0
–0.3
–1
–1
Max.
Output HIGH Voltage V
CC
= Min.,
I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
80
90
20
2.0
–0.3
–1
–1
-10
Min.
Max.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
75
85
20
mA
-12
Min.
Max.
Unit
V
V
V
V
µA
µA
mA
Automatic CE
Max. V
CC
, CE > V
IH
;
Power-down Current V
IN
> V
IH
or
—TTL Inputs
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
Automatic CE
Power-down Current CE > V
CC
– 0.3V,
—CMOS Inputs
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
I
SB2
Com’l/Ind’l
10
10
10
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
Thermal Resistance
[3]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[3]
Thermal Resistance
(Junction to Case)
[3]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
All Packages
TBD
TBD
Unit
°C/W
°C/W
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05475 Rev. *B
Page 2 of 9
PRELIMINARY
AC Test Loads and Waveforms
[4]
8-ns devices:
OUTPUT
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
10-, 12-ns devices:
Z = 50Ω
3.3V
CY7C1049DV33
R 317Ω
30 pF*
OUTPUT
30 pF
R2
351Ω
(a)
High-Z characteristics:
3.0V
90%
GND
10%
ALL INPUT PULSES
90%
10%
3.3V
OUTPUT
5 pF
(b)
R 317Ω
R2
351Ω
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
AC Switching Characteristics
[5]
Over the Operating Range
-8
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[7, 8]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[7, 8]
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[7, 8]
8
6
6
0
0
6
4
0
3
4
0
8
10
7
7
0
0
7
5
0
3
5
3
4
0
10
12
8
8
0
0
8
6
0
3
6
0
4
3
5
0
12
3
8
4
0
5
3
6
100
8
8
3
10
5
0
6
100
10
10
3
12
6
100
12
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-10
Max.
Min.
-12
Max.
Unit
Write Cycle
[9, 10]
Notes:
4. AC characteristics (except High-Z) for 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
POWER
gives the minimum amount of time that the power supply should be at stable, typical V
CC
values until the first memory access can be performed.
7. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±200
mV from steady-state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, t
HZBE
is less than t
LZBE
, and t
HZWE
is less than t
LZWE
for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05475 Rev. *B
Page 3 of 9
PRELIMINARY
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[11]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Conditions
[12]
CY7C1049DV33
Min.
2.0
Max
10
Unit
V
mA
ns
ns
0
t
RC
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
Notes:
11. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
µs
or stable at V
CC(min.)
> 50
µs
12. No input may exceed V
CC
+ 0.3V.
V
DR
> 2V
3.0V
t
R
Document #: 38-05475 Rev. *B
Page 4 of 9
PRELIMINARY
Switching Waveforms
Read Cycle No. 1
[13, 14]
CY7C1049DV33
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[14, 15]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
I
CC
HIGH
IMPEDANCE
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
[16, 17]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 18
t
HZOE
Notes:
13. Device is continuously selected. OE, CE = V
IL
.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
16. Data I/O is high-impedance if OE = V
IH
.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. During this period the I/Os are in the output state and input signals should not be applied.
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51mcu
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