Changes to Applications section................................................. 1
Changes to General Description ................................................ 1
Changes to Specifications ............................................................ 4
Changes to Timing Specifications .............................................. 5
Changes to Timing Example ..................................................... 19
9/03—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD7452
AD7452–SPECIFICATIONS
V
DD
= 2.7 V to 3.6 V, f
SCLK
= 10 MHz, f
S
= 555 kSPS, V
REF
= 2.0 V; V
DD
= 4.75 V to 5.25 V, f
SCLK
= 10 MHz, f
S
= 555 kSPS, V
REF
= 2.5 V;
V
CM1
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
3
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise
3
Intermodulation Distortion (IMD)
3
Second-Order Terms
Third-Order Terms
Aperture Delay
3
Aperture Jitter
3
Full Power Bandwidth
3, 4
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
3
Differential Nonlinearity (DNL)
3
Zero-Code Error
3
Positive Gain Error
3
Negative Gain Error
3
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
V
IN+
V
IN–
DC Leakage Current
Input Capacitance
REFERENCE INPUT
V
REF
Input Voltage
Test Conditions/Comments
f
IN
= 100 kHz
V
DD
= 4.75 V to 5.25 V, –86 dB typ
V
DD
= 2.7 V to 3.6 V, –84 dB typ
V
DD
= 4.75 V to 5.25 V, –86 dB typ
V
DD
= 2.7 V to 3.6 V, –84 dB typ
fa = 90 kHz, fb = 110 kHz
B Version
2
70
–76
–74
–76
–74
–89
–89
5
50
20
2.5
12
±1
± 0.95
±6
±2
±2
V
IN+
– V
IN–
V
CM1
± V
REF
/2
V
CM1
± V
REF
/2
±1
30/10
2.5
6
2.0
7
±1
10/30
2.4
0.8
±1
10
2.8
2.4
0.4
±1
10
Twos Complement
Unit
dB min
dB max
dB max
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
V
µA max
pF typ
V
V
µA max
pF typ
V min
V max
µA max
pF max
V min
V min
V max
µA max
pF max
@ –3 dB
@ –0.1 dB
Guaranteed no missed codes to 12 bits
2 × V
REF 5
V
CM
= V
REF
V
CM
= V
REF
When in track/hold
V
DD
= 4.75 V to 5.25 V (±1% tolerance for
specified performance)
V
DD
= 2.7 V to 3.6 V (±1% tolerance for
specified performance)
When in track/hold
DC Leakage Current
V
REF
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN 8
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
8
Output Coding
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
= 4.75 V to 5.25 V, I
SOURCE
= 200 µA
V
DD
= 2.7 V to 3.6 V, I
SOURCE
= 200 µA
I
SINK
= 200 µA
Rev. B | Page 3 of 28
AD7452
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
3
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD9, 10
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Test Conditions/Comments
1.6 µs with a 10 MHz SCLK
Sine wave input
Step input
B Version
2
16
200
290
555
Unit
SCLK cycles
ns max
ns max
kSPS max
Range: 3 V + 20%/–10%;
5 V ± 5%
SCLK on or off
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
SCLK on or off
V
DD
= 5 V, 1.55 mW typ for 100 kSPS
9
V
DD
= 3 V, 0.64 mW typ for 100 kSPS
9
V
DD
= 5 V, SCLK on or off
V
DD
= 3 V, SCLK on or off
2.7/5.25
0.5
1.5
1.2
1
7.25
3.3
5
3
V min/V max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
1
2
Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 23 and Figure 24.
Temperature ranges as follows: B Version: –40°C to +85°C.
3
See Terminology section.
4
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
5
Because the input spans of V
IN+
and V
IN–
are both V
REF
and are 180° out of phase, the differential voltage is 2 × V
REF.
6
The AD7452 is functional with a reference input from 100 mV; for V
DD
= 5 V, the reference can range up to 3.5 V.
7
The AD7452 is functional with a reference input from 100 mV; for V
DD
= 3 V, the reference can range up to 2.2 V.
8
Guaranteed by characterization.
9
See Power vs. Throughput Rate section.
10
Measured with a midscale dc input.
Rev. B | Page 4 of 28
AD7452
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a 1.6 V voltage
level. See Figure 2 and the Serial Interface section.
V
DD
= 2.7 V to 3.6 V, f
SCLK
= 10 MHz, f
S
= 555 kSPS, V
REF
= 2.0 V; V
DD
= 4.75 V to 5.25 V, f
SCLK
= 10 MHz, f
S
= 555 kSPS, V
REF
= 2.5 V;
V
CM1
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
f
SCLK 2
t
CONVERT
t
QUIET
t
1
t
2
t
33
t
43
t
5
t
6
t
7
t
8 4
t
POWER-UP5
Limit at T
MIN
, T
MAX
10
10
16 × t
SCLK
1.6
60
10
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
Unit
kHz min
MHz max
µs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
Description
t
SCLK
= 1/f
SCLK
Minimum quiet time between the end of a serial read and the next falling edge of CS
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
t
1
CS
t
2
SCLK
1
2
3
4
t
5
5
t
CONVERT
B
13
14
15
16
SDATA
0
0
0
4 LEADING ZEROS
0
DB11
DB10
DB2
DB1
DB0
t
QUIET
THREE-STATE
Figure 2. Serial Interface Timing Diagram
1
2
Common-mode voltage.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V, or 0.4 V or 2.0 V for V
DD
= 3 V.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
8
, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
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