74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Rev. 03 — 15 October 2007
Product data sheet
1. General description
The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four
address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent
inputs/outputs (Y0 to Y15) and a common input/output (Z).
The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with
one side connected to an independent input/output (Y0 to Y15) and the other side
connected to a common input/output (Z).
With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low
impedance ON-state). All unselected switches are in the high-impedance OFF-state.
With pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins
S0 to S3.
The analog inputs/outputs (Y0 to Y15, and Z) can swing between V
CC
as a positive limit
and GND as a negative limit. V
CC
to GND may not exceed 10 V.
2. Features
I
Low ON resistance:
N
80
Ω
(typical) at V
CC
= 4.5 V
N
70
Ω
(typical) at V
CC
= 6.0 V
N
60
Ω
(typical) at V
CC
= 9.0 V
I
Typical ‘break before make’ built-in
3. Applications
I
Analog multiplexing and demultiplexing
I
Digital multiplexing and demultiplexing
I
Signal gating
NXP Semiconductors
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC4067
74HC4067N
74HC4067D
74HC4067DB
74HC4067PW
74HC4067BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP24
SO24
SSOP24
TSSOP24
plastic dual in-line package; 24 leads (600 mil);
reverse bending
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT101-1
SOT137-1
SOT340-1
SOT355-1
SOT815-1
Description
Version
Type number
DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5
×
5.5
×
0.85 mm
DIP24
SO24
SSOP24
TSSOP24
plastic dual in-line package; 24 leads (600 mil);
reverse bending
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
74HCT4067
74HCT4067N
74HCT4067D
74HCT4067DB
74HCT4067PW
74HCT4067BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SOT101-1
SOT137-1
SOT340-1
SOT355-1
SOT815-1
DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5
×
5.5
×
0.85 mm
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
2 of 29
NXP Semiconductors
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
5. Functional diagram
10
11
14
13
0
16
×
3
G16
0
15
9
S0
S1
S2
S3
10
11
14
13
8
7
6
5
4
3
2
23
22
21
20
19
18
17
E
15
1
Z
16
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
15
1
MUX/DMUX
9
0
8
1
7
2
6
3
5
4
4
5
3
6
2
7
23
8
22
9
21
10
20
11
19
12
18
13
17
14
16
15
001aag726
001aag725
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Yn
V
CC
V
CC
Z
from
logic
GND
001aag729
Fig 3. Schematic diagram (one switch)
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
3 of 29
NXP Semiconductors
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
9 Y0
8 Y1
S0 10
7 Y2
6 Y3
S1 11
5 Y4
4 Y5
S2 14
3 Y6
2 Y7
S3 13
1-OF-16
DECODER
23 Y8
22 Y9
21 Y10
20 Y11
19 Y12
18 Y13
17 Y14
E 15
16 Y15
1 Z
001aag727
Fig 4. Functional diagram
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
4 of 29
NXP Semiconductors
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Y0
Y1
Y2
Y3
Y4
S0
Y5
Y6
Y7
S1
Y8
Y9
Y10
S2
Y11
Y12
Y13
S3
Y14
Y15
E
Z
001aag728
Fig 5. Logic diagram
74HC_HCT4067_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 October 2007
5 of 29
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