Agilent ADCS-1021, ADCS-2021
CMOS Image Sensors
Data Sheet
Key Specifications and Features
• High quality, low cost CMOS image
sensors
• Industry-standard 32-pin CLCC
package
Description
The ADCS-1021 and ADCS-2021
CMOS Image Sensors capture
high quality, low noise images
while consuming very low power.
These parts integrate a highly
sensitive active pixel photodiode
array with timing control and
onboard A/D conversion. Avail-
able in either VGA (640x480) or
CIF (352x288) resolution image
arrays, the devices are ideally
suited for a wide variety of
applications.
The ADCS-2021 and ADCS-1021,
when coupled with compatible
image processors from either
Agilent or selected Agilent
partners, provide a complete
imaging system to enable rapid
end-product development.
Designed for low-cost consumer
electronic applications, the
ADCS-2021 and ADCS-1021
sensors deliver unparalleled
performance for mainstream
imaging applications.
ADCS-2021 (VGA) and
ADCS-1021 (CIF) are CMOS active
pixel image sensors with inte-
grated A/D conversion and full
timing control. They provide
random access of sensor pixels,
which allows windowing and
panning capabilities. The sensor
is designed for video conferencing
applications and still image
capabilities. The ADCS family
achieves excellent image quality
with very low dark current, high
sensitivity, and superior anti-
blooming characteristics. The
devices operate from a single DC
bias voltage, are easy to configure
and control, and feature low
power consumption.
Programmable Features
• Programmable window size ranging
from the full array down to a 4 x 4
pixel window
• Programmable panning capability
which allows a specified window
(minimum 4x4 pixels) to be located
anywhere on the sensor array
• Integrated programmable gain
amplifiers with independent gain
control for each color (R, G, B)
• Internal register set programmable
via either the UART or Synchronous
serial interface
• Integrated timing controller with
rolling electronic shutter, row/
column addressing, and operating
mode selection with programmable
exposure control, frame rate, and
data rate
• Programmable horizontal, vertical,
and shutter synchronization signals
• Programmable horizontal and
vertical blanking intervals
• VGA resolution (640H x 480V)–
ADCS-2021
• CIF resolution (352H x 288V)–
ADCS-1021
• High frame rates for digital video
VGA: 15 frames/second
CIF: 30 frames/second
• High sensitivity, low noise design
ideal for capturing high-quality
images in a variety of lighting
conditions
• Integrated analog-to-digital
converters:
VGA (ADCS-2021): 10 bit, programmable
CIF (ADCS-1021): 8 bit, fixed
• Parallel and serial output
• Automated, dark response
compensation
• Automatic subtraction of column
fixed pattern noise
• Still image capability
• Synchronous serial or UART
interface
• Integrated voltage references
Applications
• Digital still camera
• PC camera
• Handheld computers
• Cellular phones
• Notebook computers
• Toys
Brief Introduction
The Agilent ADCS-2021 and
Agilent ADCS-1021 image sen-
sors act as normal CMOS digital
devices from the outside. Inter-
nal circuits are a combination of
sensitive analog and timing
circuits. Therefore, the designer
must pay attention to the PC
board layout and power supply
design. Writing to registers via an
I
2
C compatible two-wire interface
provides control of the sensor.
Sensor data is normally output
via an 8 or 10 bit parallel inter-
face (serial data output is also
available). Once the registers are
programmed the sensor is self-
clocking and all timing is inter-
nally generated. On chip pro-
grammable amplifiers provide a
way to separately adjust the red
green and blue pixels for a good
white balance. Analog to digital
conversion is also on chip and 8
or 10 bit digital data is output. A
data ready pulse follows each
valid pixel output. An end of row
signal follows each row and an
end of frame signal follows each
frame.
PCB Layout
Analog Vdd and analog ground
need to be routed separately
from digital V
dd
and digital
ground. Noisy circuits or ICs
should not be placed on the
opposite side of the PC board.
Heat producing circuits such as
microprocessors or LCD displays
should not be placed next to or
opposite from the sensor to
reduce noise in the image.
Power Supply
The sensor operates at 3.3 VDC.
There are two power supplies for
the sensor. Analog V
dd
and
Digital V
dd
. The two supplies and
grounds must be kept separate.
Two separate regulators provide
the best isolation. Any noise on
the analog supply will result in
noise in the image. Analog and
digital ground should be tied
together at a single point of
lowest impedance and noise.
Master Clock
The part requires a 50% duty cycle
master clock. Maximum clock
rates are 25 MHz for ADCS-2021
and 32 MHZ for ADCS-1021.
Reset
A hard reset is required before
the sensor will function properly.
Once the master clock is running,
assert nRST_nSTBY for 40 clock
cycles.
Register Communication
Communication (read/write) to
the sensor registers is via a two
wire serial interface—either a
synchronous I
2
C compatible or
half duplex UART (9600 baud
default). nTristate (pin 3
ADCS-1021 only) must be pulled
high for normal operation. The
ADCS-2021 does not have
nTristate.
Parallel Data Output
8 or 10 bit parallel data is output
from the sensor. A data ready
line (DRDY) is asserted when the
data is valid. The sensor acts as a
master in the way it outputs
data. There is no flow control or
data received handshake. Once
the RUN bit (CONTROL register)
is set, the image processor must
be ready to accept data at the
sensor rate and when the data is
presented.
Serial Data Output
In this mode, output data lines
D0 and D1 (the lower two bits of
the parallel data port) act as a
two wire serial interface.
Handshaking
At the end of one row of data, the
nROW line is asserted. At the end
of one frame of data, the
nFRAME_nSYNC line is asserted.
Registers
On the next page is a table of
sample register settings (see
Figure 1). These values are a
good starting point.
2
Table 1. Register Set Declaration for Agilent ADCS-1021 and ADCS-2021 Image Sensors.
Register Name
Identifications Register
Status Register
Interrupt Mask Register
Pad Control Register
Pad Drive Control Register
Interface Control Register
Interface Timing Register
Baud Fraction Register
Baud Rate Register
ADC Control Register
First Window Row Register
First Window Column Register
Last Window Row Register
Last Window Column Register
Timing Control Register
PGA Gain Register: Green
PGA Gain Register: Red
PGA Gain Register: Blue
PGA Gain Register: Green
Row Exposure Low Register
Row Exposure High Register
Sub-Row Exposure Register
Error Control Register
Interface Timing 2 Register
Interface Control 2 Register
Horizontal Blank Register
Vertical Blank Register
Configuration Register
Control Register
Reserved
Reserved
Reserved
Reserved
Mnemonic
IDENT
STATUS
IMASK
PCTRL
PDRV
ICTRL
ITMG
BFRAC
BRATE
ADCCTRL
FWROW
FWCOL
LWROW
LWCOL
TCTRL
ERECPGA
EROCPGA
ORECPGA
OROCPGA
ROWEXPL
ROWEXPH
SROWEXP
ERROR
ITMG2
ICTRL2
HBLANK
VBLANK
CONFIG
CONTROL
Address (hex)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
Sample Value (hex)
0x7F
0x00
0x03
0x00
0x20
0x00
0x00
0x00
0x08
0x00
0x07
0x79
0xA8
0x04
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00
0x4B
0x00
0x00
0x00
0x0C
0x04
—
—
—
—
3
Setting Exposure and Gain
The exposure of an image is a
function of the exposure and
gain registers. Exposure sets the
length of time each pixel inte-
grates the light (shutter speed).
Gain settings allow pixel values
to be amplified. Gain values from
1x to 40x are allowed, but higher
gain settings amplify noise (much
like higher ISO film speeds are
grainier). It is best to use the
lower gain settings for better
images. Gains from 1x to 10x are
generally recommended.
Note in Table 2, there are two
green gain registers, one for the
odd number row green pixels and
one for the even number row
green pixels. The green color
filters can be slightly different
between rows and this allows
fine-tuning. Using the same gain
setting for both green registers is
usually enough. Since the blue
channel is not as sensitive, using
blue gains approximately double
that of red and green will allow
the A/D full range on all three
channels.
Using a MacBeth Color Checker is
a good way to judge exposure and
color balance. A good raw image
will have a good grey scale (the
bottom patches on the chart).
Gain settings should be adjusted
so the red, green, and blue values
are equal on any one grey patch.
After setting gain, the exposure
registers should be adjusted for a
good exposure. There are three
exposure registers (see Table 3).
Table 2. PGA Gain Register Settings.
Register Name
PGA Gain Register: Green
PGA Gain Register: Red
PGA Gain Register: Blue
PGA Gain Register: Green
Mnemonic
ERECPGA
EROCPGA
ORECPGA
OROCPGA
Address (hex)
0x0F
0x10
0x11
0x12
Table 3. Row Exposure Register Settings.
Register Name
Row Exposure Low Register
Row Exposure High Register
Sub-Row Exposure Register
Mnemonic
ROWEXPL
ROWEXPH
SROWEXP
Address (hex)
0x13
0x14
0x15
The row exposure high register
(upper 8 bits) and row exposure
low register (lower 8 bits) act as
a single 16 bit register. This
16 bit register sets the integra-
tion time (shutter speed) of the
sensor. The sub-row exposure
register is used for very small
changes to exposure and allow
fine-tuning for exact shutter
speeds.
Proper exposure will result in
black values near 0x00 and white
values near 0xFF (assuming
8 bits). All six grey patches on the
MacBeth chart should have
different average intensity values
in the image. If the two brightest
patches both appear white then
the exposure is too long. If the
two darkest patches both appear
black then the exposure is too
short. Remember that the raw
image does not have gamma
correction applied yet. The final
grey scale image needs to be
evaluated after gamma correction.
Image Processing
The raw data from the sensor
requires image processing before
a digital image is ready for
viewing. Some standard steps of
image processing are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Defective pixel correction
Lens flare subtraction
Auto-exposure
Auto-white balance
Color filter array interpolation
(demosaic)
Color correction (3x3 matrix)
Gamma correction
Color space correction (3x3
matrix)
Data compression
Image processing is not part of
the sensor and must be supplied
separately. Image processors
that are compatible with these
sensors are available from Agilent
Technologies and selected Agilent
partners.
4
Typical Application
30 MHz
Clock
27
Clk
12
IMODE0
11 IMODE1
Vdd
10K
3
nTRISTATE
D0
D1
D2
D3
D4
D5
D6
D7
DRDY
2
1
30
29
28
21
20
19
26
13
14
9
18
17
D0
D1
D2
D3
D4
D5
D6
D7
DATA READY
Reset
End of Row
End of Frame
TxD/RxD
Clock
Parallel Interface
ADCS-1021
nRST_nSTBY
nROW
nFRAME_nSYNC
NC
NC
10
4
nIRQ
NC
Analog Analog Digital Digital
Vdd GND
GND
Vdd
23, 8,
22, 7,
25, 32, 24, 31, 5
16
15
6
3.3V
Regulator
3.3V
Regulator
Serial Interface
Host System
Star Ground
Typical Electrical Specifications
Part Number
Pixel size
Maximum Clock Rate
Effective Sensor Dynamic Range
Effective Noise Floor
Dark Signal
[1,3]
Saturation Voltage
Full Well Capacity
Conversion Gain
[2]
Programmable Gain Range
Fill Factor
Exposure Control
Supply Voltage
Absolute Max. Power Supply Voltage
Absolute Max. DC Input Voltage (any pin)
Power Consumption (typical)
Power Consumption (max)
Optical Format
Operating Temperature
Storage Temperature
Notes:
1. Specified over complete pixel area
2. Measured at unity gain
3. Excludes dark current shot noise
ADCS-2021 (VGA)
7.4 x 7.4
µm
25 MHz (VGA)
65 dB (VGA)
43 e-
240 e-/sec (@ 22°C)
1.22 V
68,000 e-
17
µV/e-
1– 40 (8 bit resolution)
42%
0.5
µsec
minimum, 0.5
µsec
increments
3.3 V, -5%/+10%
3.6 V
3.6 V
150 mW operating, 150
µW
standby
200 mW operating, 3.3 mW standby
1/3”
-5° to +65°C
-40° to +125°C
ADCS-1021 (CIF)
7.4 x 7.4
µm
32 MHz (CIF)
61 dB (CIF)
43 e-
240 e-/sec (@ 22°C)
1.22 V
68,000 e-
17
µV/e-
1– 40 (8 bit resolution)
42%
0.5
µsec
minimum, 0.5
µsec
increments
3.3 V, -5%/+10%
3.6 V
3.6 V
150 mW operating, 150
µW
standby
200 mW operating, 3.3 mW standby
1/4”
-5° to +65°C
-40° to +125°C
5
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