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74ABT74D,112

Description
74ABT74 - Dual D-type flip-flop with set and reset; positive edge-trigger SOIC 14-Pin
Categorylogic    logic   
File Size222KB,13 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric View All

74ABT74D,112 Overview

74ABT74 - Dual D-type flip-flop with set and reset; positive edge-trigger SOIC 14-Pin

74ABT74D,112 Parametric

Parameter NameAttribute value
Brand NameNexperia
Is it Rohs certified?conform to
MakerNexperia
Parts packaging codeSOIC
package instructionSOP,
Contacts14
Manufacturer packaging codeSOT108-1
Reach Compliance Codecompliant
Samacsys Description74ABT74 - Dual D-type flip-flop@en-us
seriesABT
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Humidity sensitivity level1
Number of digits1
Number of functions2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Maximum supply current (ICC)0.05 mA
propagation delay (tpd)4 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width3.9 mm
minfmax150 MHz
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 3 — 12 October 2020
Product data sheet
1. General description
The 74ABT74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP),
set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored
in the flip-flop and appear at the Q output. This device is fully specified for partial power down
applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
Supply voltage range from 4.5 V to 5.5 V
BiCMOS high speed and output drive
Direct interface with TTL levels
Power-up 3-state
I
OFF
circuitry provides partial Power-down mode operation
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74ABT74D
74ABT74PW
-40 °C to +85 °C
-40 °C to +85 °C
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
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