Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
FEATURES
•
Low static and dynamic power dissipation with high speed and
high output drive
The 74ABT853 is an octal transceiver with a parity
generator/checker and is intended for bus–oriented applications.
When Output Enable A (OEA) is High, it will place the A outputs in a
high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a latch. The error data
can then be passed, stored, cleared, or sampled depending on the
ENABLE and CLEAR control signals.
If both OEA and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
•
Open-collector ERROR output
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•
Power-up 3-State
•
Live insertion/extraction permitted
DESCRIPTION
The 74ABT853 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
3.4
7.4
4
7
50
UNIT
ns
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT853 N
74ABT853 D
74ABT853 DB
74ABT853 PW
NORTH AMERICA
74ABT853 N
74ABT853 D
74ABT853 DB
74ABT853PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
LOGIC SYMBOL
OEA
1
24 V
CC
23 B0
22 B1
2
3
4
5
6
7
8
9
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 PARITY
14 OEB
13 ENABLE
TOP VIEW
23
22
21
20
19
18
17
16
14
1
11
13
A0 A1 A2 A3 A4 A5 A6 A7
OEB
OEA
CLEAR
ENABLE
B0 B1 B2 B3 B4 B5 B6 B7
PARITY
ERROR
15
10
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
ERROR 10
CLEAR 11
GND 12
SA00262
SA00263
1995 Sep 06
1
853-1672 15702
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
PIN DESCRIPTION
SYMBOL
A0 – A7
B0 – B7
OEA
OEB
PARITY
ERROR
CLEAR
ENABLE
GND
V
CC
PIN NUMBER
2, 3, 4, 5, 6, 7, 8, 9
23, 22, 21, 20, 19, 18, 17, 16
1
14
15
10
11
13
12
24
NAME AND FUNCTION
A port 3–State inputs/outputs
B port 3–State inputs/outputs
Enables the A outputs when Low
Enables the B outputs when Low
Parity output/input
Error output (open collector)
Clears the error flag register when Low
Enable input (active-Low)
Ground (0V)
Positive supply voltage
FUNCTION TABLE
INPUTS
MODE
A data to B bus and generate odd parity output
B data to A bus and check for parity error
1
A bus and B bus disabled
2
A data to B bus and generate inverted parity output
OEB
L
H
H
L
OEA
H
L
H
L
An
Σ
OF HIGHS
Odd
Even
(output)
X
Odd
Even
Bn + PARITY
Σ
OF HIGHS
(output)
X
X
(output)
An
(input)
Bn
Z
(input)
OUTPUTS
Bn
An
(input)
Z
An
PARITY
L
H
(input)
Z
H
L
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
MODE
Pass
ENABLE
L
CLEAR
L
Bn + PARITY
Σ
OF HIGHS
Odd
Even
Odd
Even
X
X
X
INTERNAL NODE
POINT ”P”
H
L
H
L
X
X
X
OUTPUT
PRE–STATE
ERRORn–1
X
H
X
L
X
L
H
ERROR
OUTPUT
H
L
H
L
L
H
L
H
Sample
Clear
Store
H
L
X
Z
=
=
=
=
L
H
H
H
L
H
High voltage level steady state
Low voltage level steady state
Don’t care
High impedance ”off” state
1995 Sep 06
2
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
LOGIC DIAGRAM
8
A0 – A7
8
B0 – B7
8
OEB
PARITY
OEA
8
8
MUX
9–bit
Odd
Parity
Tree
”P”
A
}
}
B
9
Sel A/B
ERROR
ENABLE
CLEAR
SA00264
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1995 Sep 06
3
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
4.5
0
2.0
0.8
–32
64
5
+85
LIMITS
MAX
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
Min
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High–level output voltage
All outputs except ERROR
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
I
I
I
OFF
I
PU/PD
I
IH
+ I
OZH
I
IL
+ I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
Quiescent supply current
Low-level output voltage
Input leakage
current
Control pins
Data pins
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don’t care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
Outputs enabled, one input at 3.4V,
other inputs at V
CC
or GND; V
CC
= 5.5V
∆I
CC
Additional supply current per
input pin
2
Outputs 3-State, one data input at 3.4V,
other inputs at V
CC
or GND; V
CC
= 5.5V
Outputs 3-State, one enable input at 3.4V,
other inputs at V
CC
or GND; V
CC
= 5.5V
–50
2.5
3.0
2.0
Typ
–0.9
3.5
4.0
2.6
0.42
±0.01
±5
±5.0
±5.0
5.0
–5.0
5.0
–100
0.5
25
0.5
0.5
0.01
0.5
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
38
50
1.5
50
1.5
–50
Max
–1.2
2.5
3.0
2.0
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
38
50
1.5
50
1.5
T
amb
= –40°C
to +85°C
Min
Max
–1.2
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
mA
µA
mA
UNIT
Power-off leakage current
Power-up/down 3-State
output current
3
3-State output High current
3-State output Low current
Output high leakage current
Output current
1
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V
CC
between 0V and 2.1V, with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10%, a
transition time of up to 100µsec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design.
1995 Sep 06
4
Philips Semiconductors
Product specification
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
74ABT853
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORMS
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Propagation delay
OEA to PARITY
Propagation delay
CLEAR to ERROR
Propagation delay
ENABLE to ERROR
Propagation delay
Bn or PARITY to ERROR
Output enable time
OEA to An or OEB to Bn, PARITY
Output disable time
OEA to An or OEB to Bn, PARITY
4
1, 4
1, 4
3
4
1, 4
2, 5
2, 5
1.2
1.0
2.1
2.5
1.8
2.3
1.0
1.8
1.8
2.0
3.0
1.0
2.1
3.1
3.2
T
amb
= +25
o
C
V
CC
= +5.0V
Typ
3.4
2.6
7.4
7.4
6.6
6.7
3.6
3.8
4.5
7.9
9.0
3.2
4.1
5.1
5.6
Max
4.8
4.0
9.5
9.7
8.5
8.6
5.5
5.1
5.8
10.1
11.5
5.1
5.8
7.3
7.2
T
amb
= –40 to +85
o
C
V
CC
= +5.0V
±10%
Min
1.2
1.0
2.1
2.5
1.8
2.3
1.0
1.8
1.8
2.0
3.0
1.0
2.1
3.1
3.2
Max
5.3
4.5
11.2
11.0
10.5
10.0
6.2
6.0
6.6
11.7
12.8
6.2
6.7
7.9
8.1
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
AC SETUP REQUIREMENTS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORMS
T
amb
= +25
o
C
V
CC
= +5.0V
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
h
(L)
t
w
(L)
t
w
(L)
Setup time, High or Low
Bn or PARITY to ENABLE
Hold time, High or Low
Bn or PARITY to ENABLE
Setup time, High
CLEAR to ENABLE
Hold time, Low
CLEAR to ENABLE
Pulse width, Low
CLEAR
Pulse width, Low
ENABLE
6
6
6
6
3
6
8.5
8.5
0.0
0.0
2.0
3.0
3.5
4.0
TYP
6.5
3.6
–3.4
–6.3
–1.6
1.8
1.0
2.5
T
amb
= –40 to +85
o
C
V
CC
= +5.0V
±10%
MIN
8.5
8.5
0.0
0.0
2.0
3.0
3.5
4.0
ns
ns
ns
ns
ns
ns
UNIT
1995 Sep 06
5
Embedded System
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