EEWORLDEEWORLDEEWORLD

Part Number

Search

531JC139M000DG

Description
CMOS Output Clock Oscillator, 139MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531JC139M000DG Overview

CMOS Output Clock Oscillator, 139MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531JC139M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency139 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
physical size7.0mm x 5.0mm x 1.85mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Zero-copy problem with multi-port network cards
I have already realized zero copy of single-port network card, that is, the network card DMAs the data packet into the ring. My question now is whether the data packets received by several ports of mu...
liehu_4061 Embedded System
How to read circuit diagrams Recommended resources 4. Teach you how to read "analog circuit diagrams"
[align=center][size=5]How to read circuit diagrams Recommended resources 4. [color=rgb(0, 0, 0)][font=微软雅黑]Teach you how to read "analog circuit diagrams"[/font][/color][/size][/align] [color=#000][fo...
tiankai001 Download Centre
GD32VF103V-EVAL Review——by littleshrimp
@littleshrimpThe first GD32VF103 project Create a GD32VF103 project using Visual Studio Code Use NucleiStudio to import GD32VF103_Demo_Suites routine GD32VF103V_EVAL uses USB to serial port function G...
okhxyyo Domestic Chip Exchange
A brief discussion on the dropout and power consumption of low dropout linear regulators (LDO)
This paper discusses Low Dropout Line Regulator( LDO)fundamental principle and Dropout,Power Dissipation...
frozenviolet Analog electronics
Select problem in VxWorks (who has used select to send and receive TCP or Udp data)
[code] while(true){ assert(errno==0);//The error number here is equal to 0 int ret=select(nfds+1,&readFs,NULL,NULL,&timeOut); if( ret>0 ){ assert(errno==0x3d0002);//It must be 0x3d0002 (S_objLib_OBJ_U...
walkincloud517 Real-time operating system RTOS
How to read and write FPGA RAM in SoC ARM
I want to read and write the RAM on the FPGA side on the arm side, but I don't know what function to use to read and write, alt_write_word, alt_read_word, is it possible? If it is possible, how to rea...
flyingcool FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 701  2764  345  1848  1514  15  56  7  38  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号