DSM2180F3
DSM (Digital Signal Processor System Memory)
For Analog Devices ADSP-218X Family (5V Supply)
FEATURES SUMMARY
s
Glueless Connection to DSP
– Easily add memory, logic, and I/O to DSP
s
Figure 1. Packages
128K Byte Flash Memory
– For Bootloading and/or Data Overlay Memory
– Programmable Decoding and Paging Logic
allows accessing Flash memory as Byte DMA
(BDMA) and as External Data Overlay mem-
ory
– Rapidly access Flash memory with BDMA for
booting and loading internal DSP Overlay
memory. Alternatively access the same Flash
memory as External Data Overlay memory to
efficiently write Flash memory with code up-
dates and data, a byte at a time with no DMA
setup overhead
– Individual 16K Byte Flash memory sectors
match size of DSP External Data Overlay
window for efficient data management. Inte-
grated page logic provides easy DSP access
to all 128K Bytes.
– DSM connects to lower byte of 16-bit DSP
data bus. Byte-wide accesses to 8-bit BDMA
space. Half-word accesses to 16-bit Data
Memory Overlay and 16-bit I/O Mem space.
s
PQFP52 (T)
PLCC52 (K)
In-System Programming (ISP) with JTAG
– Program entire chip in 10-20 seconds with no
involvement of the DSP
– Eliminate sockets for pre-programmed mem-
ory and logic devices
– Efficient manufacturing allows easy product
testing and Just-In-Time inventory
– Use low-cost FlashLINK
TM
cable with PC
s
s
5V Devices (±10%)
Up to 16 Multifunction I/O Pins
– Increase total DSP system I/O capability
– I/O controlled by DSP software or PLD logic
– 8mA I/O pin drive at 5 Vcc
s
Content Security
– Programmable Security Bit blocks access of
device programmers and readers
s
General purpose PLD
– Over 3,000 Gates of PLD with 16 macro cells
– Use for peripheral glue logic to keypads, con-
trol panel, displays, LCD, UART devices, etc.
– Eliminate PLDs and external logic devices
– Create state machines, chip selects, simple
shifters and counters, clock dividers, delays
– Simple PSDsoft Express
TM
software ...Free
s
Zero-Power Technology
– 75
µA
standby at V
CC
=5V
Small Packaging
– 52-pin PQFP or 52-pin PLCC
Memory Speed
– 90 ns
1/63
s
s
December 2001
DSM2180F3
TABLE OF CONTENTS
Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DSP Address/Data/Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programmable Logic (PLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Runtime Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
JTAG ISP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Security and NVM Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Specifying Mem Map with PSDsoft ExpressTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DSM Security Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/63
DSM2180F3
DSP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Port B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power On Reset, Warm Reset, Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Programming In-Circuit using JTAG ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1
AC/DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table:
Table:
Table:
Table:
Table:
Table:
Table:
Table:
Table:
Table:
Table:
Table:
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Reset (Reset) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table:
Table:
Table:
Table:
Table:
PLCC52 - 52 lead Plastic Leaded Chip Carrier, rectangular . . . . . . . . . . . . . . . . . . . . . . . . 57
Assignments – PLCC52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PQFP52 - 52 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Pin Assignments – PQFP52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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DSM2180F3
SUMMARY DESCRIPTION
These are system memory devices for use with
Digital Signal Processors from the popular Analog
Devices ADSP-218X family. DSM means Digital
signal processor System Memory. A DSM device
brings in-system programmable Flash memory,
programmable logic, and additional I/O to DSP
systems. The result is a simple and flexible two-
chip solution for DSP designs. DSM devices pro-
vide the flexibility of Flash memory and smart
JTAG programming techniques for both manufac-
turing and the field. On-chip integrated memory
decode logic and memory paging logic make it
easy to add large amounts of external Flash mem-
ory to the ADSP-218X family for bootloading upon
power-up and/or overlay memory. The DSP ac-
cesses this Flash memory using either its Byte
DMA (BDMA) interface or as external data overlay
memory (no DMA setup overhead).
Figure 2. PLCC Connections
CNTL2
RESET
CNTL1
CNTL0
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
product and manage inventory by rapidly pro-
gramming test code, then application code as de-
termined by inventory requirements (Just-In Time
inventory). Additionally, JTAG ISP reduces devel-
opment time by turning fast iterations of DSP code
in the lab. Code updates in the field require no dis-
assembly of product. The FlashLINK
TM
JTAG pro-
gramming cable costs $59 USD and plugs into any
PC or note-book parallel port.
Figure 3. PQFP Connections
PD2 1
PD1 2
PD0 3
PC7 4
PC6 5
PC5 6
PC4 7
V
CC
8
GND 9
PC3 10
PC2 11
40 CNTLO
41 RESET
43 CNTL1
42 CNTL2
46 GND
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
47 PB5
45 PB6
44 PB7
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 V
CC
30 AD7
29 AD6
28 AD5
27 AD4
4
7
5
3
2
52
51
50
49
48
47
6
PC1 12
1
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
46
45
44
43
42
41
40
39
38
37
36
35
34
27
28
29
31
32
30
33
AD15
AD14
PC0 13
PA7 14
PA6 15
PA5 16
PA4 17
PA3 18
GND 19
PA2 20
PA1 21
PA0 22
AD0 23
AD1 24
AD2 25
AD12
AD11
AD10
AD9
AD8
VCC
AD7
AD6
AD5
AD4
AD3 26
AD13
AI02858
AI02857
JTAG In-System Programming (ISP) reduces de-
velopment time, simplifies manufacturing flow,
and lowers the cost of field upgrades. The JTAG
ISP interface eliminates the need for sockets and
pre-programmed memory and logic devices. For
manufacturing, end products may be assembled
with a blank DSM device soldered to the circuit
board and programmed at the end of the manufac-
turing line in 10 to 20 seconds with no involvement
of the DSP. This allows efficient means to test
In addition to ISP Flash memory, DSM devices
add programmable logic (PLD) and up to 16 con-
figurable I/O pins to the DSP system. The state of
each I/O pin can be driven by DSP software or
PLD logic. PLD and I/O configuration are program-
mable by JTAG ISP, just like the Flash memory.
The PLD consists of more than 3000 gates and
has 16 macro cell registers. Common uses for the
PLD include chip selects for external devices (i.e.
UART), state-machines, simple shifters and
counters, keypad and control panel interfaces,
clock dividers, handshake delay, muxes, etc. This
eliminates the need for small external PLDs and
logic devices. Configuration of PLD, I/O, and Flash
memory mapping are easily entered in a point-
and-click environment using the software develop-
ment tool, PSDsoft Express
TM
. This software is
available at no charge from www.psdst.com.
PA7
PA6
PA5
PA4
PA3
PA1
PA0
PA2
AD1
AD2
4/63
GND
AD0
AD3
DSM2180F3
Figure 4. System Block Diagram, Two-Chip Solution
I/O, PLD, CHIP SELECTS
ISP, I/O, PLD, CHIP SEL
AI04910
8 I/O
PORTS
DSM2180F3
DSP SYSTEM MEMORY
ADDR & DECODE LOGIC
8 I/O
PORTS
I/O BUS
POWER MANAGEMENT
MEM PAGE CONTROL
WR, RD, BMS, DMS, IOMS
22 ADDRESS
8 DATA
13 FLAGS / 4 INTR
SERIAL
DEVICE
ADSP-218X
FAMILY
ANALOG
DEVICES
DSP
The two-chip combination of a DSP and a DSM
device is ideal for systems which have limitations
on size, EMI levels, and power consumption. DSM
memory and logic are “zero-power”, meaning they
automatically go to standby between memory ac-
cesses or logic input changes, producing low ac-
tive and standby current consumption, which is
ideal for battery powered products.
5/63
SERIAL
DEVICE
CONTENT SECURITY
16 MACROCELL PLD
FLASH MEMORY
128k X 8
I/O CONTROL
JTAG
ISP TO
ALL
AREAS
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