FIN1022 2 X 2 LVDS High Speed Crosspoint Switch
September 2001
Revised December 2001
FIN1022
2 X 2 LVDS High Speed Crosspoint Switch
General Description
This non-blocking 2x2 crosspoint switch has a fully differ-
ential input to output data path for low noise generation and
low pulse width distortion. The device can be used as a
high speed crosspoint switch, 2:1 multiplexer, 1:2 demulti-
plexer or 1:2 signal splitter. The inputs can directly interface
with LVDS and LVPECL levels.
Features
s
Low jitter, 800 Mbps full differential data path
s
Worst case jitter of 190ps
with PRBS
=
2
23
−
1 data pattern at 800 Mbps
s
Rail-to-rail common mode range is 0.5V to 3.25V
s
Worst case power dissipation is less than 126 mW
s
Open-circuit fail safe protection
s
Fast switch time of 1.1 ns typical
s
35 ps typical pin channel to channel skew
s
3.3V power supply operation
s
Non-blocking switch
s
LVDS receiver inputs accept LVPECL signals directly
s
7.5 kV HBM ESD protection
s
16-lead SOIC package and TSSOP package
s
Inter-operates with TIA/EIA 644-1995 specification
s
See the Fairchild Interface Solutions web page for cross
reference information:
www.fairchildsemi.com/products/interface/lvds.html
Ordering Code:
Order Number
FIN1022M
FIN1022MTC
Package Number
M16A
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500653
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FIN1022
Connection Diagram
Pin Descriptions
Pin Name
R
IN0+
, R
IN1+
R
IN0−
, R
IN1−
Description
LVDS non-inverting data inputs
LVDS inverting data inputs
D
OUT0+
, D
OUT1+
LVDS non-inverting data outputs
D
OUT0−
, D
OUT1−
LVDS inverting data outputs
EN
0
EN
1
SEL
0
SEL
1
V
CC
GND
LVTTL input for enabling D
OUT0+
/D
OUT0−
LVTTL input for enabling D
OUT1+
/D
OUT1−
LVTTL input for selecting R
IN0+
/R
IN0−
or
R
IN1+
/R
IN1−
for output D
OUT0+
/D
OUT0−
LVTTL input for selecting R
IN0+
/R
IN0−
or
R
IN1+
/R
IN1−
for output D
OUT1+
/D
OUT1−
Power Supply
Ground
Function Table
Inputs
SEL
0
L/O
L/O
H
H
X
X
L/O
H
X
O
=
OPEN
Outputs
EN
1
H
H
H
H
H
H
L/O
L/O
L/O
D
OUT0+
R
IN0+
R
IN0+
R
IN1+
R
IN1+
Z
Z
R
IN0+
R
IN1+
Z
D
OUT0−
R
IN0−
R
IN0−
R
IN1−
R
IN1−
Z
Z
R
IN0−
R
IN1−
Z
D
OUT1+
R
IN0+
R
IN1+
R
IN0+
R
IN1+
R
IN0+
R
IN1+
Z
Z
Z
L
=
LOW Logic Level
SEL
1
L/O
H
L/O
H
L/O
H
X
X
X
EN
0
H
H
H
H
L/O
L/O
H
H
L/O
D
OUT1−
R
IN0−
R
IN1−
R
IN0−
R
IN1−
R
IN0−
R
IN1−
Z
Z
Z
1:2 Splitter
Repeater
Switch
1:2 Splitter
Mode
D
OUT0
Disabled
D
OUT0
Disabled
D
OUT1
Disabled
D
OUT1
Disabled
D
OUT0
and D
OUT1
Disabled
X
=
Don’t Care
Z
=
High Impedance
L / O
=
LOW or OPEN
H
=
HIGH Logic Level
Function Diagrams
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2
FIN1022
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Driver Short Circuit Current (I
OSD
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
−
0.3V to
+
4.6V
−
0.3V to
+
4.6V
−
0.3V to
+
4.6V
Continuous
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Operating Temperature (T
A
)
Electrostatic Discharge
(HBM 1.5 k
Ω
, 100 pF)
Electrostatic Discharge
(MM 0
Ω
, 100 pF)
3.0V to 3.6V
0 to V
CC
−
40
°
C to
+
85
°
C
>
7500V
>
300V
−
65
°
C to
+
150
°
C
150
°
C
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified (Note 2)
Symbol
Parameter
Test Conditions
Min
Typ
(Note 3)
270
285
365
365
475
440
35
1.0
1.2
1.45
35
±10
±20
−10
−10
100
−100
0.05
V
IN
=
GND
V
IN
=
V
CC
LVTTL Control Characteristics
V
IH
V
IL
I
IN
V
IK
I
PU/PD
C
IN
C
OUT
I
CC
Input High Voltage
Input Low Voltage
Input Current
Input Clamp Voltage
Output Power-Up/Power-Down
High Z Leakage Current
Input Capacitance
Output Capacitance
Power Supply Current
No Load, All Drivers Enabled
R
L
=
75
Ω,
All Drivers Enabled
R
L
=
75
Ω,
All Drivers Enabled
Note 2:
This part will only function with datasheet specification when a resistive load is applied to the driver outputs.
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Max
Units
LVDS Differential Driver Characteristics
V
OD
Output Differential Voltage
R
L
=
75
Ω,
See Figure 3
R
L
=
75
Ω,
See Figure 3
T
A
=
25°C and V
CC
=
3.3V
∆V
OD
V
OS
∆V
OS
I
OZD
I
OFF
I
OS
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
Disabled Output Leakage Current
Power-Off Current
Short Circuit Output Current
R
L
=
75
Ω,
See Figure 3
See Figure 3
See Figure 3
V
OUT
=
3.6V or GND, Driver Disabled
V
CC
=
0V, V
IN
or V
OUT
=
3.6V or 0V
V
OUT
=
0V, Driver Enabled
V
OUTx
+
=
0V, V
OUTx
−
=
0V, Driver Enabled
LVDS Differential Receiver Characteristics
V
TH
V
TL
V
IC
I
IND
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Common Mode Voltage
Input Current (Differential Inputs)
V
IC
=
0.05V or 1.2V or 3.25V
V
CC
=
3.3V
mV
V
µA
mV
mV
V
mV
µA
µA
mA
3.25
±20
±20
2
0.8
V
IN
=
3.6V or GND
I
IK
= −18
mA
V
CC
=
0V to 1.5V
4.5
4.5
35
35
35
−1.5
±10
±20
V
V
µA
V
µA
pF
pF
mA
mA
mA
Device Characteristics
3
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FIN1022
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
PLH
t
PHL
t
ZHD
t
ZLD
t
HZD
t
LZD
t
SET
t
HOLD
t
JIT
f
TOG
t
SKEW
Parameter
Differential Output Propagation Delay
LOW-to-HIGH
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
Selection Propagation Delay
LOW-to-HIGH (SEL
n
to OUT
n
)
Selection Propagation Delay
HIGH-to-LOW (SEL
n
to OUT
n
)
Differential Output Enable Time
from Z-to-HIGH
Differential Output Enable Time
from Z-to-LOW
Differential Output Disable Time
from HIGH-to-Z
Differential Output Disable Time
from LOW-to-Z
Input (IN
n
+
/IN
n
−
) Setup Time to SEL
n
Input (IN
n
+
/IN
n
−
) Hold Time to SEL
n
Output Peak-to-Peak Jitter
Maximum Toggle Frequency
Within Device Channel-to-Channel Skew
Pulse Skew |t
PLHD
-t
PHLD
|
Part-to-Part Skew (Note 5)
Note 4:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Note 5:
Part-to-part skew is the maximum delay time difference on like edges (LOW-to-HIGH or HIGH-to-LOW) for the same V
CC
and temperature condi-
tions.
Test Conditions
Min
0.7
Typ
(Note 4)
Max
1.6
Units
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
R
L
=
75
Ω,
C
L
=
5 pF,
V
CC
=
3.3V, T
A
=
25°C
See Figure 4 and Figure 5
1.0
0.7
1.0
290
290
0.6
1.2
1.2
1.3
1.6
1.3
580
580
1.5
R
L
=
75
Ω,
C
L
=
5 pF,
V
CC
=
3.3V, T
A
=
25°C
See Figure 6 and Figure 7
0.9
0.6
0.9
1.1
1.1
1.2
1.5
1.2
3.5
3.5
3.5
3.5
R
L
=
75Ω, C
L
=
5 pF
See Figure 8 and Figure 9
See Figure 10
See Figure 10
2
23
−1
PRBS Sequence at 800 Mbps
50% Duty Cycle at 800 Mbps
R
L
=
75
Ω,
C
L
=
5 pF, See Figure 4
0.5
0.5
0.3
0.3
190
20
35
80
225
500
ps
ps
Mbps
ps
ps
ps
800
900
35
0
100
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4
FIN1022
Required Specifications
1. When the true and complement LVDS outputs (having
a 75
Ω
connected between outputs) are connected to
3.75 k
Ω
resistors and the common point of those 3.75
k
Ω
resistors are connected to a voltage source that
sweeps from 0 to 2.4V, the DC V
OD
and
∆
V
OD
are still
maintained (see Figure 1).
2. When the true and complement LVDS outputs (having
a 5 pF capacitor attached between outputs) are con-
nected with 37.5
Ω
resistors each to common point,
then the common point does not vary by more than 150
mV under all process, temperature and voltage condi-
tions when the outputs switch either from LOW-to-
HIGH or from HIGH-to-LOW (see Figure 2).
3. Pull-down resistors are required on Enable (EN
0
and
EN
1
) and select (SEL
0
and SEL
1
) inputs.
4. Fail safe protection on the outputs that draw less than
20
µ
A of current (worst case) on the LVDS inputs. In
this condition, if the input is in fail safe selected to
OUT
0+
/OUT
0−
(say) and the outputs are Enabled then
OUT
0+
=
HIGH and OUT
0−
=
LOW. This prevents noise
from being amplified when the connection is broken.
5. In the disabled state the outputs can go beyond V
CC
but there should be no appreciable leakage (see I
OZD
and I
OFF
specifications)
FIGURE 1. Common Mode Supply Test Circuit
FIGURE 2. Dynamic V
OS
Test Circuit and Waveforms
5
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