MC74HCT125A
Quad 3-State Noninverting
Buffer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
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The MC74HCT125A is identical in pinout to the LS125. The device
inputs are compatible with standard CMOS and LSTTL outputs.
The MC74HCT125A noninverting buffer is designed to be used
with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low.
Features
MARKING
DIAGRAMS
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
HCT125AG
AWLYWW
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7A Requirements
Chip Complexity: 72 FETs or 18 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
•
These are Pb−Free Devices
PIN ASSIGNMENT
OE1
A1
Y1
OE2
A2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
OE4
A4
Y4
OE3
A3
Y3
A2
OE2
A3
A1
OE1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HCT
125A
ALYWG
G
A
=
Assembly Location
L, WL
=
Wafer Lot
Y, YY
=
Year
W, WW =
Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
LOGIC DIAGRAM
Active−Low Output Enables
2
1
5
4
9
10
12
13
PIN 14 = V
CC
PIN 7 = GND
11
Y4
8
Y3
6
Y2
3
Y1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
FUNCTION TABLE
HCT125A
Inputs
A
H
L
X
OE
L
L
H
Output
Y
H
L
Z
OE4
OE3
A4
©
Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 2
Publication Order Number:
MC74HCT125A/D
MC74HCT125A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
Value
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±
20
±
35
±
75
500
450
– 65 to + 150
260
Unit
V
V
V
mA
mA
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
V
CC
+ 125
1000
500
400
Unit
V
V
_C
ns
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2
MC74HCT125A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output
Voltage
Maximum Low−Level Output
Voltage
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
Maximum Quiescent Supply Current
(per Package)
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
mA
V
out
= 0.1 V
|I
out
|
v
20
mA
V
in
= V
IH
|I
out
|
v
20
mA
V
in
= V
IH
V
OL
V
in
= V
IL
|I
out
|
v
20
mA
V
in
= V
IL
I
in
I
OZ
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
|I
out
|
v
6.0 mA
|I
out
|
v
6.0 mA
V
CC
V
4.5 to
5.5
4.5 to
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
– 55 to
25_C
2.0
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±
0.1
±
0.5
v
85_C
2.0
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±
1.0
±
5.0
v
125_C
2.0
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±
1.0
±
10
mA
mA
V
Unit
V
V
V
I
CC
5.5
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns, V
CC
= 5.0 V
±
10%)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
TLH
,
t
THL
C
in
C
out
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
Maximum Input Capacitance
Maximum 3−State Output Capacitance (Output in High−Impedance State)
V
CC
V
5.0
5.0
5.0
5.0
−
−
– 55 to
25_C
18
24
18
12
10
15
v
85_C
23
30
23
15
10
15
v
125_C
27
36
27
18
10
15
Unit
ns
ns
ns
ns
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
30
pF
ORDERING INFORMATION
Device
MC74HCT125ADG
MC74HCT125ADR2G
NLV74HCT125ADR2G*
MC74HCT125ADTG
MC74HCT125ADTR2G
NLVHCT125ADTR2G*
TSSOP−14
(Pb−Free)
SOIC−14
(Pb−Free)
Package
Shipping
†
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
96 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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3
MC74HCT125A
SWITCHING WAVEFORMS
V
CC
V
M
GND
HIGH
IMPEDANCE
10%
t
PZH
t
THL
OUTPUT Y
V
M
t
PHZ
90%
V
OL
V
OH
HIGH
IMPEDANCE
t
r
INPUT A (V
I
)
t
PLH
OUTPUT Y
90%
V
M
10%
t
TLH
V
I
= GND to 3.0 V
V
M
= 1.3 V
90%
V
M
10%
t
f
V
CC
GND
t
PHL
OE (V
I
)
OUTPUT Y
V
M
Figure 1.
Figure 2.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL.
CONNECT TO GND WHEN
TESTING t
PHZ
and t
PZH.
C
L
*
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
V
CC
OE
A
Y
(1/4 OF THE DEVICE)
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4
MC74HCT125A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
−A−
14
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P
7 PL
0.25 (0.010)
M
B
M
1
7
G
C
R
X 45
_
F
DIM
A
B
C
D
F
G
J
K
M
P
R
−T−
SEATING
PLANE
D
14 PL
0.25 (0.010)
M
K
T B
S
M
A
S
J
SOLDERING FOOTPRINT*
7X
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
_
7
_
0.228 0.244
0.010 0.019
7.04
1
14X
14X
1.52
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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