SSTUB32866
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
with parity for DDR2-800 RDIMM applications
Rev. 04 — 15 April 2010
Product data sheet
1. General description
The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. The register is configurable (using
configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter
configuration can be designated as Register A or Register B on the DIMM.
The SSTUB32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
The SSTUB32866 is packaged in a 96-ball, 6
×
16 grid, 0.8 mm ball pitch LFBGA package
(13.5 mm
×
5.5 mm).
2. Features and benefits
Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications
Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
Controlled output impedance drivers enable optimal signal integrity and speed
Meets or exceeds SSTUB32866 JEDEC standard speed performance
Supports up to 450 MHz clock frequency of operation
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
Supports SSTL_18 data inputs
Checks parity on the DIMM-independent data inputs
Partial parity output and input allows cascading of two SSTUB32866s for correct parity
error processing
Differential clock (CK and CK) inputs
Supports LVCMOS switching levels on the control and RESET inputs
Single 1.8 V supply operation (1.7 V to 2.0 V)
Available in 96-ball, 13.5 mm
×
5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
400 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality
NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
4. Ordering information
Table 1.
Ordering information
Solder process
Package
Name
SSTUB32866EC/G
SSTUB32866EC/S
Description
Version
Type number
Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
ball compound)
96 balls; body 13.5
×
5.5
×
1.05 mm
Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
ball compound)
96 balls; body 13.5
×
5.5
×
1.05 mm
4.1 Ordering options
Table 2.
Ordering options
Temperature range
T
amb
= 0
°C
to +70
°C
T
amb
= 0
°C
to +85
°C
Type number
SSTUB32866EC/G
SSTUB32866EC/S
SSTUB32866_4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2010
2 of 30
NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
5. Functional diagram
RESET
CK
CK
VREF
DCKE
SSTUB32866
1D
C1
R
QCKEA
QCKEB
(1)
DODT
1D
C1
R
QODTA
QODTB
(1)
DCS
1D
C1
R
QCSA
QCSB
(1)
CSR
D2
0
1
1D
C1
R
Q2A
Q2B
(1)
to 10 other channels
(D3, D5, D6, D8 to D14)
002aac010
(1) Disabled in 1 : 1 configuration.
Fig 1.
Functional diagram of SSTUB32866; 1 : 2 Register A configuration with C0 = 0
and C1 = 1 (positive logic)
SSTUB32866_4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2010
3 of 30
NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUB32866EC/G
SSTUB32866EC/S
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aac011
ball A1
index area
Transparent top view
Fig 3.
Pin configuration for LFBGA96
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DCKE
D2
D3
DODT
D5
D6
PAR_IN
CK
CK
D8
D9
D10
D11
D12
D13
D14
2
PPO
D15
D16
QERR
D17
D18
RESET
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
3
VREF
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
VREF
4
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
DD
5
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS
n.c.
Q8
Q9
Q10
Q11
Q12
Q13
Q14
6
DNU
Q15
Q16
DNU
Q17
Q18
C0
DNU
n.c.
Q19
Q20
Q21
Q22
Q23
Q24
Q25
002aab108
Fig 4.
Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
SSTUB32866_4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2010
5 of 30
京公网安备 11010802033920号
EEWORLD
