pin is grounded. IN0 = +1 V dc, IN1 = –1 V dc. SELECT input is driven with 0 V to +5 V pulse. Measure transition time from 50% of the SELECT input value
(+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa.
2
ENABLE
pin is driven with 0 V to +5 V pulse (with 3 ns edges). State of SELECT input determines which channel is activated (i.e., if SELECT = Logic 0, IN0 is selected). Set
IN0 = +1 V dc, IN1 = –1 V dc, and measure transition time from 50% of
ENABLE
pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5,
∆t
OFF
is the disable
time,
∆t
ON
is the enable time.
3
All inputs are grounded. SELECT input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the SELECT input termination will lower glitch, as does increasing R
L
.
4
Decreasing R
L
lowers the bandwidth slightly. Increasing C
L
lowers the bandwidth considerably (see Figure 19).
5
A resistor (R
S
) placed in series with the mux inputs serves to optimize 0.1 dB flatness, but is not required. Increasing output capacitance will increase peaking and reduce band-
width (see Figure 20.)
6
Select input which is not being driven (i.e., if SELECT is Logic 1, input activated is IN1); drive all other inputs with V
IN
= 0.707 V rms and monitor output at ƒ = 5 and 30 MHz.
R
L
= 1 kΩ (see Figure 13).
7
Mux is disabled (i.e.,
ENABLE
= Logic 1) and all inputs are driven simultaneously with V
IN
= 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. R
L
= 30
Ω
to simulate
R
ON
of one enabled mux within a system (see Figure 14). In this mode the output impedance is very high (typ 10 M
Ω),
and the signal couples across the package; the load imped-
ance determines the crosstalk.
8
Voltage gain decreases for lower values of R
L
. The resistive divider formed by the mux enabled output resistance (27
Ω)
and R
L
causes a gain which decreases as R
L
decreases
(i.e., the voltage gain is approximately 0.97 V/V (3% gain error) for R
L
= 1 kΩ).
9
Larger values of R
L
provide wider output voltage swings, as well as better gain accuracy. See Note 8.
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Embedded System
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