DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output
July 15, 2009
DAC121S101QML
12-Bit Micro Power Digital-to-Analog Converter with Rail-
to-Rail Output
General Description
The DAC121S101 is a full-featured, general purpose 12-bit
voltage-output digital-to-analog converter (DAC) that can op-
erate from a single +2.7 V to 5.5 V supply and consumes just
177 µA of current at 3.6 V. The on-chip output amplifier allows
rail-to-rail output swing and the three wire serial interface op-
erates at clock rates up to 20 MHz over the specified supply
voltage range and is compatible with standard SPI™, QSPI,
MICROWIRE and DSP interfaces.
The supply voltage for the DAC121S101 serves as its voltage
reference, providing the widest possible output dynamic
range. A power-on reset circuit ensures that the DAC output
powers up to zero volts and remains there until there is a valid
write to the device. A power-down feature reduces power
consumption to less than a microWatt.
The low power consumption and small packages of the
DAC121S101 make it an excellent choice for use in battery
operated equipment.
The DAC121S101 operates over the extended temperature
range of -55°C to +125°C.
Features
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Total Ionizing Dose
100 krad(Si)
Single Event Latch-up
120 MeV-cm
2
/mg
Guaranteed Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to Zero Volts Output
SYNC Interrupt Facility
Wide power supply range (+2.7 V to +5.5 V)
Small Packages
Power Down Feature
Key Specifications
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Resolution
12 bits
DNL
+0.21, -0.10 LSB (typ)
Output Settling Time
12.5 µs (typ)
Zero Code Error
2.1 mV (typ)
Full-Scale Error
−0.04 %FS (typ)
Power Dissipation
—
Normal Mode 0.52 mW (3.6 V) / 1.19 mW (5.5 V) typ
0.014 µW (3.6 V) / 0.033 µW (5.5 V) typ
—
Pwr Down
Mode
Applications
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Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Programmable Attenuators
Ordering Information
NS PART NUMBER
DAC121S101WGRQV
(Note 12)
SMD PART NUMBER
5962R0722601VZA
100 krad(Si)
NS PACKAGE NUMBER
WG10A
PACKAGE DISCRIPTION
10LD Ceramic SOIC
SPI™ is a trademark of Motorola, Inc.
© 2009 National Semiconductor Corporation
300180
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DAC121S101QML
Connection Diagrams
10LD Ceramic SOIC
30018001
Top View
See NS Package Number WG10A
Block Diagram
30018003
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2
DAC121S101QML
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage, V
A
6.5 V
Voltage on any Input Pin
−0.3 V to (V
A
+ 0.3 V)
Input Current at Any Pin (Note 3)
10 mA
Maximum Output Current (Note 10)
10 mA
V
OUT
Pin in Powerdown Mode
1.0 mA
Package Input Current (Note 3)
20 mA
Power Dissipation at T
A
= 25°C
See (Note 4)
Maximum Junction Temperature
175°C
Lead Temperature
Ceramic SOIC
(Soldering 10 Seconds)
260°C
Storage Temperature
−65°C to +150°C
Package Weight (Typical)
Ceramic SOIC
220 mg
ESD Tolerance (Note 5)
Class 3A (5000 V)
Operating Ratings
(Notes 1, 2)
Operating Temperature Range
Supply Voltage, V
A
Any Input Voltage (Note 6)
Output Load
SCLK Frequency
−55°C to +125°C
+2.7 V to 5.5 V
−0.1 V to (V
A
+ 0.1 V)
0 to 1500 pF
Up to 20 MHz
Package Thermal Resistance
Package
10-lead Ceramic SOIC
Package on 2 layer, 1oz.
PCB
θ
JA
(Still Air)
214°C/W
θ
JC
25.7°C/W
Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup
1
2
3
4
5
6
7
8A
8B
9
10
11
12
13
14
Description
Static tests at
Static tests at
Static tests at
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Setting time at
Setting time at
Setting time at
Temp (° C)
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
3
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DAC121S101QML
DAC121S101 Electrical Characteristics
DC Parameters
The following specifications apply for V
A
= +2.7 V to +5.5 V, R
L
=
∞
, C
L
= 200 pF to GND, f
SCLK
= 20 MHz, input code range 48 to
4047.
Boldface limits apply for T
MIN
≤
T
A
≤
T
MAX
: all other limits T
A
= 25°C, unless otherwise specified.
Symbol
Parameter
Conditions
Notes
Typical
(Note 8)
Min
Max
Units
Sub-
groups
STATIC PERFORMANCE
Resolution
Monotonicity
INL
DNL
ZE
FSE
GE
ZCED
TC GE
Integral Non-Linearity
Differential Non-Linearity
Zero Code Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Error Tempco
V
A
= 3 V
V
A
= 5 V
Over Decimal codes 48 to 4047
V
A
= 2.7 V to 5.5 V
I
OUT
= 0
I
OUT
= 0
All ones Loaded to DAC register
(Note
9)
(Note
9)
(Note
9)
(Note
9)
V
A
= 3 V, I
OUT
= 10 µA
ZCO
Zero Code Output
V
A
= 3 V, I
OUT
= 100 µA
V
A
= 5 V, I
OUT
= 10 µA
V
A
= 5 V, I
OUT
= 100 µA
V
A
= 3 V, I
OUT
= 10 µA
FSO
Full Scale Output
V
A
= 3 V, I
OUT
= 100 µA
V
A
= 5 V, I
OUT
= 10 µA
V
A
= 5 V, I
OUT
= 100 µA
Maximum Load
Capacitance
DC Output Impedance
R
L
=
∞
R
L
= 2 kΩ
(Note
9)
2.0
4
2
4
2.997
2.991
4.994
4.992
1500
1500
8
16
2.990
2.985
4.985
4.985
0
(Note
9)
(Note
9)
±2.75
+0.21
−0.10
+2.12
−0.04
−0.11
−20
−0.7
−1.0
−0.7
+15
−1.0
±1.0
12
12
−8.0
8.0
+1.0
Bits
Bits
LSB
LSB
LSB
mV
%FSR
%FSR
µV/°C
ppm/°C
ppm/°C
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
OUTPUT CHARACTERISTICS
IPD
SINK
Vout Pin in Powerdown
Mode
Output Voltage Range
All PD Modes
1.0
V
A
6
10
8
9
mA
V
mV
mV
mV
mV
V
V
V
V
pF
pF
Ω
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
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4
DAC121S101QML
DC Parameters (Continued)
The following specifications apply for V
A
= +2.7 V to +5.5 V, R
L
=
∞
, C
L
= 200 pF to GND, f
SCLK
= 20 MHz, input code range 48 to
4047.
Boldface limits apply for T
MIN
≤
T
A
≤
T
MAX
: all other limits T
A
= 25°C, unless otherwise specified.
Symbol
LOGIC INPUT
I
IN
V
IL
V
IH
C
IN
Input Current
Input Low Voltage
Input High Voltage
Input Capacitance
V
A
= 5 V
V
A
= 3 V
V
A
= 5 V
V
A
= 3 V
(Note
9)
Normal Mode
f
SCLK
= 20 MHz
Normal Mode
f
SCLK
= 10 MHz
Supply Current (output
unloaded)
Normal Mode
f
SCLK
= 0
All PD Modes,
f
SCLK
= 20 MHz
All PD Modes,
f
SCLK
= 10 MHz
All PD Modes,
f
SCLK
= 0
Normal Mode
f
SCLK
= 20 MHz
Normal Mode
f
SCLK
= 10 MHz
Normal Mode
Power Consumption (output f
SCLK
= 0
unloaded)
All PD Modes,
f
SCLK
= 20 MHz
All PD Modes,
f
SCLK
= 10 MHz
All PD Modes,
f
SCLK
= 0
I
OUT
/ I
A
Power Efficiency
I
LOAD
= 2 mA
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
3.6 V
(Note
9)
(Note
9)
(Note
9)
(Note
9)
(Note
9)
(Note
9)
(Note
9)
(Note 11)
Notes
Typical
.02
.002
Min
Max
±2
±5
Units
LSB
μs
Sub-
groups
5
2.4
2.1
6
−200 +200
0.8
0.5
nA
V
V
V
V
pF
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Parameter
Conditions
Notes
Typical
(Note 8)
Min
Max
Units
Sub-
groups
POWER REQUIREMENTS
216
145
185
132
150
115
22
12
12
6
.006
.004
1.19
0.52
1.02
0.47
0.82
0.41
0.12
0.07
0.04
0.02
0.033
0.014
91
94
270
200
230
175
190
160
60
30
40
20
1.0
1.0
1.49
.72
1.27
.63
1.05
.58
.33
.11
.22
.08
5.5
3.6
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
µW
µW
%
%
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
I
A
P
C
Burn In Delta Parameters
Symbol
INL
ts
Parameter
Integral non-linearity
Output voltage settling time
T
A
@ 25°C
Conditions
T
A
= 25°C
T
A
= 25°C
5
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