D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
PCI1410A GHK/GGU/PGE
PC Card Controllers
Data Manual
NOTE
Designing with this device may require extensive support. Before incorporating this device into
a design, customers should contact TI or an Authorized TI Distributor.
2000
PCIBus Solutions
SCPS057
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright
2000, Texas Instruments Incorporated
Contents
Section
1
Title
Page
1–1
1–1
1–1
1–2
1–2
1–2
2–1
3–1
3–1
3–2
3–2
3–2
3–2
3–3
3–3
3–3
3–4
3–5
3–6
3–6
3–7
3–7
3–8
3–8
3–10
3–10
3–11
3–11
3–11
3–13
3–14
3–15
3–15
3–16
3–17
3–18
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . .
3.4.1
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . .
3.5
PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
PC Card Insertion/Removal and Recognition . . . . . . . . . . .
3.5.2
P
2
C Power-Switch Interface (TPS2211) . . . . . . . . . . . . . . .
3.5.3
Zoomed-Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4
Ultrazoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6
Integrated Pullup Resistors for PC Card Interface . . . . . . .
3.5.7
SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . .
3.5.8
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . .
3.5.9
PC Card-16 Distributed DMA Support . . . . . . . . . . . . . . . . .
3.5.10
PC Card-16 PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.11
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Serial Bus-Interface Implementation . . . . . . . . . . . . . . . . . . .
3.6.2
Serial Bus-Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . .
3.6.4
Accessing Serial Bus Devices Through Software . . . . . . . .
3.7
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
PC Card Functional and Card Status Change Interrupts .
3.7.2
Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3
Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
iii
4
3.7.5
Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . .
3.7.6
SMI Support in the PCI1410A Device . . . . . . . . . . . . . . . . . .
3.8
Power-Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1
Clock-Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2
CardBus PC Card Power Management . . . . . . . . . . . . . . . .
3.8.3
16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . .
3.8.4
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.5
Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . .
3.8.6
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.7
PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8
CardBus Device Class Power Management . . . . . . . . . . . .
3.8.9
ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.10
Master List of PME Context Bits and
Global Reset-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . .
4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register . . . . . . . . .
4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18
3–18
3–19
3–19
3–19
3–19
3–20
3–21
3–21
3–22
3–23
3–23
3–24
4–1
4–1
4–2
4–2
4–3
4–4
4–5
4–5
4–5
4–6
4–6
4–6
4–7
4–7
4–8
4–9
4–9
4–9
4–10
4–10
4–11
4–11
4–12
4–12
4–13
4–14
4–15
4–15
4–15
4–16
iv