iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG
32Mx72 DDR SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR SDRAM Data Rate = 200, 250, 266, 333Mbps
Package:
•
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Industrial, Enhanced and Military Temperature
Ranges
Organized as 32M x 72/80
Weight: AS4DDR32M72PBG </= 3.10 grams typical
* This product and or it’s specifications is subject to change without notice.
BENEFITS
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
•
34% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Configuration Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
32 Meg x 72
8 Meg x 16 x 4 Banks
8K
8K (A0 A12)
4 (BA0 BA1)
1K (A0 A9)
AS4DDR32M72PBG
Rev. 1.4 07/10
Micross Components reserves the right to change products or specifications without notice.
1
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG
SDRAM-DDR PINOUT TOP VIEW
DQ0
DQ1
DQ3
DQ6
DQ7
CA S0\
CS0\
VSS
VSS
CLK3\
NC
DQ2
DQ4
DQ5
DQML0
WE0\
RAS0\
VSS
VSS
CKE3
CLK3
DQ14
DQ12
DQ10
DQ8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ55
DQ53
DQ51
DQ49
DQ15
DQ13
DQ11
DQ9
VSS
VSS
VCC
VCCQ
VSS
VSS
VCC
VSSQ
A9
A0
A2
A12
A10
A7
A5
DNU
BA0
A11
A6
A4
DNU
BA1
A8
A1
A3
DNU
VCCQ
VCC
VSS
VSS
VCCQ
VCC
VSS
VSS
VREF
RAS1\
CAS1\
VCC
VCC
CLK2\
DQSL2
CKE4 DQMH4
DQ73
DQ75
DQ77
DQ79
CLK4
DQ72
DQ74
DQ76
DQ78
CAS4\
DQ71
DQ69
DQ67
DQ65
WE4\
DQ70
DQ68
DQ66
DQ64
RAS4\
CS4\
DQ16
DQ18
DQ20
DQ22
DQML1
WE1\
CS1\
VSS
VSS
CKE2
CLK2
DQMH2
DQ17
DQ19
DQ21
DQ23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ40
DQ42
DQ44
DQ46
DQ31
DQ29
DQ27
DQ26
NC
DQMH1
CLK1\
VCCQ
VCCQ
RAS2\
WE2\
DQML2
DQ37
DQ36
DQ34
DQ32
VSS
DQ30
DQ28
DQ25
DQ24
CLK1
CKE1
VCC
VCC
CS2\
CAS2\
DQ39
DQ38
DQ35
DQ33
VCC
DQMH0 DQSH3 DQSL0 DQSH0
CLK0
CKE0
VCCQ
VCCQ
CS3\
CAS3\
WE3\
DQ54
DQ52
DQ50
DQ48
DQSL3
CLKO\
VSS
VSS
DQSL4
RAS3\
DQML3
DQSL1 DQSH1
DQ56 DQMH3
DQ57
DQ60
DQ62
VSS
DQ58
DQ59
DQ61
DQ63
DQSH4 CLK4\
VSS
VCC
VCCQ
VSS
VCC
VCCQ
DQML4 DQSH2\ DQ41
VCC
VSS
VSS
VCC
VSS
VSS
DQ43
DQ45
DQ47
Ground
Array Power
D/Q Power
Address
Data IO
CNTRL
Address/DNU
UNPOPULATED
AS4DDR32M72PBG
Rev. 1.4 07/10
Micross Components reserves the right to change products or specifications without notice.
2
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG
FUNCTIONAL BLOCK DIAGRAM
DQ0-15
CLK0
CLK0\
CKE0
CS0\
WE0\
RAS0\
CAS0\
DQML0
DQMH0
DQSL0
DQSH0
BA0
BA1
ADDR
VRef
VCC
VCCQ
VSS
CLK1
CLK1\
CKE1
CS1\
WE1\
RAS1\
CAS1\
DQML1
DQMH1
DQSL1
DQSH1
DQ16-
31
DQ32-47
CLK2
CLK2\
CKE2
CS2\
WE2\
RAS2\
CAS1\
DQML2
DQMH2
DQSL2
DQSH2
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
CLK3
CLK3\
CKE3
CS3\
WE3\
RAS3\
CAS3\
DQML3
DQMH3
DQSL3
DQSH3
DQ48-63
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
CLK4
CLK4\
CKE4
CS4\
WE4\
RAS4\
CAS4\
DQML4
DQMH4
DQSL4
DQSH4
DQ64-79
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
AS4DDR32M72PBG
Rev. 1.4 07/10
Micross Components reserves the right to change products or specifications without notice.
3
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG
PIN DEFINITIONS / FUNCTIONAL DESCRIPTION
BGA Locations
SYMBOL
DESCRIPTION
Clock: CKx and CKx\ are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CKx and negative edge of CKx\.
Output data (DQ's and DQS) is referenced to the crossings of the differential clock
inputs.
Clock Enable: CKE controls the clock inputs. CKE high enables, CKE Low disables
the clock input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE
is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry CKE
is Asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input buffers are disabled
during POWER-DOWN Input buffers are disabled during SELF REFRESH. CKE is an
SSTL-2 input but will detect an LVCMOS LOW level after VCC is applied
Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) contained
words. All commands are masked with CSx\ is registered HIGH. CSx\ provides for
external bank selection on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
Command Inputs: RASx, CASx and Wex\ define the command being entered.
F4, F16, G5, G15, K1, K12,
CKx, CKx\
L2, L13, N6, M8
G4, G16, K2, K13, M6
CKEx
G1, G13, K4, K16, M12
CSx\
F4, F16, G5, G15, K1, K12, RASx\, CASx\,
L2, L13, N7, M9
Wex\
G4, G16, K2, K14, M7
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DQMLx, DQMHx
DQMLx or Hx is sampled HIGH at time of a WRITE access. DM is sampled on both
edges of DQSLx and DQSHx.
BA0, BA1
Bank Address Inputs: BA0, BA1, define which bank an ACTIVE READ, WRITE or
PRECHARGE Command is being applied.
Address Input: Provide the row address for Active commands, and the column address
and auto precharge bit (A10) for READ / WRITE commands to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank or all banks.
The address inputs also provide the op-code during a MODE RESISTER SET
command.
E8, E9
A7, A8, A9, A10, B7, B8,
B9, B10, C7, C8. C9, C10, A0-11, A12
D7
A2, A3, A4, A13, A14, B1,
B2, B3, B4, B13, B14, B15,
B16, C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2, D3,
D4, D13, D14, D15, D16,
E1, E16, M1, M16, N1, N2, DQ0-79
N3, N4, N13, N14, N15,
N16, T2, T3, T4, T13, T14,
T15, N7, N8, N9, N10, P7,
P8, P9, P10, R7, R8, R9,
R10, T7, T8, T9, T10
E6, E7, E10, E11, F5, K5,
DQSLX, DQSHX
L12, N5, N12, E5
B11, B12, C5, C6, E3, F3,
G3, H3, H12, H16, J3, J12,
VCC
J16, K3, L3, M3, P11, P12,
R5, R6, T16
A11, A12, D5, D6, H4, H15,
VCCQ
J4, J15, T5, T6
A5, A6, A16, B5, B6, C11,
C12, D11, D12, E14, F14,
G14, H1, H2, H5, H13,
VSS
H14, J1, J2, J5, J13, J14,
K14, L14, P5, P6, R11.
R12, T1, T11, T12, M14
E12
AS4DDR32M72PBG
Rev. 1.4 07/10
Data I/O
Data Stobe: Output with read data, input with write data. DQS is edge-aligned with
read data, centered in write data. It is used to capture data
Core Power Supply
I/O Power Supply
Ground (Digital)
VREF
SSTL-2 Reference Voltage
Micross Components reserves the right to change products or specifications without notice.
4
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG
GENERAL DESCRIPTION
The 2.4Gb DDR SDRAM MCM, is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a quad-
bank DRAM. Each of the chip’s 134,217,728-bit banks
is organized as 8,192 rows by 1024 columns by 32 bits.
The 256MB(2.4Gb) DDR SDRAM MCM uses a DDR
architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n-prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 256MB DDR SDRAM effectively consists of a single 2n-bit
wide, one-clock-cycle data tansfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs and
by the memory contoller during WRITEs. DQS is edgealigned
with data for READs and center-aligned with data for WRITEs.
Each chip has two data strobes, one for the lower byte and
one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CLK and CLK#); the crossing of CLK going HIGH and CLK#
going LOW will be referred to as the positive edge of CLK.
Commands (address and control signals) are registered at
every positive edge of CLK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or WRITE
command are used to select the bank and the starting column
location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge function
may be enabled to provide a selftimed row precharge that is
initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a powersaving
power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0-12 select the row). The address bits
registered coincident with the READ or WRITE command
are used to select the starting column location for the burst
access.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register defi nition, command descriptions and
device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those
specified may result in undefined operation. Power must
fi
rst
be applied to V
CC
and V
CCQ
simultaneously, and then to V
REF
(and to the system V
TT
). V
TT
must be applied after V
CCQ
to avoid
device latch-up, which may cause permanent damage to the
device. V
REF
can be applied any time after V
CCQ
but is expected
to be nominally coincident with V
TT
. Except for CKE, inputs are
not recognized as valid until after V
REF
is applied. CKE is an
SSTL_2 input but will detect an LVCMOS LOW level after V
CC
is applied. Maintaining an LVCMOS LOW level on CKE during
powerup is required to ensure that the DQ and DQS outputs
will be in the High-Z state, where they will remain until driven in
normal operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200μs delay prior to applying an executable
command.
Once the 200μs delay has been satisfied, a DESELECT or NOP
command should be applied, and CKE should be brought HIGH.
Following the NOP command, a PRECHARGE ALL command
should be applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1 LOW
and BA0 HIGH) to enable the DLL, followed by another LOAD
MODE REGISTER command to the mode register (BA0/ BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required between
the DLL reset and any READ command. A PRECHARGE ALL
command should then be applied, placing the device in the all
banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed (t
RFC
must be satisfi ed.) Additionally, a LOAD MODE
REGISTER command for the mode register with the reset DLL
bit deactivated (i.e., to program operating parameters without
resetting the DLL) is required. Following
these requirements, the DDR SDRAM is ready for normal
operation.
Micross Components reserves the right to change products or specifications without notice.
AS4DDR32M72PBG
Rev. 1.4 07/10
5
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