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AS7C251MPFD18A-133TQI

Description
Standard SRAM, 1MX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
Categorystorage    storage   
File Size510KB,19 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
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AS7C251MPFD18A-133TQI Overview

Standard SRAM, 1MX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C251MPFD18A-133TQI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time3.8 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density18874368 bit
Memory IC TypeSTANDARD SRAM
memory width18
Number of functions1
Number of terminals100
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1MX18
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
February 2005
®
AS7C251MPFD18A
2.5V 1M x 18 pipelined burst synchronous SRAM
Features
Organization: 1,048,576 x18 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/3.8 ns
Fast OE access time: 3.5/3.8 ns
Fully synchronous register-to-register operation
Double-cycle deselect
Asynchronous output enable control
Available 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[19:0]
CLK
CS
CLR
Burst logic
Q
20
CS
Address
D
20
18 20
1M
x
18
Memory
array
18
18
register
CLK
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
registers
CLK
D
2
OE
CE
CLK
D
ZZ
Enable
register
Q
Output
registers
CLK
Input
registers
CLK
Power
down
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
-166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
290
85
40
-133
7.5
133
3.8
270
75
40
Units
ns
MHz
ns
mA
mA
mA
2/10/05, v. 1.2
Alliance Semiconductor
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.

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Description Standard SRAM, 1MX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 Standard SRAM, 1MX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 Standard SRAM, 1MX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100 Standard SRAM, 1MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100 Standard SRAM, 1MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100 Standard SRAM, 1MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 Standard SRAM, 1MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
Is it lead-free? Contains lead Contains lead Lead free Lead free Lead free Contains lead Contains lead
Is it Rohs certified? incompatible incompatible conform to conform to conform to incompatible incompatible
Parts packaging code QFP QFP QFP QFP QFP QFP QFP
package instruction LQFP, LQFP, LQFP, LQFP, LQFP, LQFP, LQFP,
Contacts 100 100 100 100 100 100 100
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Maximum access time 3.8 ns 3.8 ns 3.8 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns
Other features PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
JESD-30 code R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100
JESD-609 code e0 e0 e3 e3 e3 e0 e0
length 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm
memory density 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit
Memory IC Type STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM
memory width 18 18 18 18 18 18 18
Number of functions 1 1 1 1 1 1 1
Number of terminals 100 100 100 100 100 100 100
word count 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words
character code 1000000 1000000 1000000 1000000 1000000 1000000 1000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 70 °C 70 °C 70 °C 85 °C 85 °C 70 °C
organize 1MX18 1MX18 1MX18 1MX18 1MX18 1MX18 1MX18
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP LQFP LQFP LQFP LQFP LQFP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED 245 245 245 NOT SPECIFIED NOT SPECIFIED
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 2.625 V 2.625 V 2.625 V 2.625 V 2.625 V 2.625 V 2.625 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V 2.375 V 2.375 V 2.375 V 2.375 V 2.375 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL
Terminal surface TIN LEAD TIN LEAD MATTE TIN MATTE TIN MATTE TIN TIN LEAD TIN LEAD
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED 30 30 30 NOT SPECIFIED NOT SPECIFIED
width 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) - - Integrated Silicon Solution ( ISSI )
Base Number Matches - 1 1 1 1 1 -
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