MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
JFETs Switching
N–Channel — Depletion
2N5640
1 DRAIN
3
GATE
2 SOURCE
1
2
3
CASE 29–04, STYLE 5
TO–92 (TO–226AA)
Rating
Drain–Source Voltage
Drain–Gate Voltage
Reverse Gate–Source Voltage
Forward Gate Current
Total Device Dissipation @ TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Junction Temperature Range
Storage Temperature Range
Symbol
VDS
VDG
VGSR
IGF
PD
R
q
JA
TJ
Tstg
Value
30
30
30
10
350
2.8
357
– 65 to +150
– 65 to +150
Unit
Vdc
Vdc
Vdc
mAdc
mW
mW/°C
°C/W
°C
°C
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Gate–Source Breakdown Voltage (IG = 10
µAdc,
VDS = 0)
Gate Reverse Current
(VGS = –15 Vdc, VDS = 0)
(VGS = –15 Vdc, VDS = 0, TA = 100°C)
Drain Cutoff Current
(VDS = 15 Vdc, VGS = –6.0 Vdc)
(VDS = 15 Vdc, VGS = –6.0 Vdc, TA = 100°C)
V(BR)GSS
IGSS
—
—
ID(off)
—
—
1.0
1.0
nAdc
µAdc
1.0
1.0
nAdc
µAdc
30
—
Vdc
ON CHARACTERISTICS
Zero–Gate–Voltage Drain Current(1)
(VDS = 20 Vdc, VGS = 0)
Drain–Source On–Voltage
(ID = 3.0 mAdc, VGS = 0)
Static Drain–Source On Resistance
(ID = 1.0 mAdc, VGS = 0)
1. Pulse Test: Pulse Width
IDSS
VDS(on)
rDS(on)
5.0
—
—
—
0.5
100
mAdc
Vdc
Ohms
v
300
m
s, Duty Cycle
v
3.0%.
REV 1
4–130
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2N5640
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted) (Continued)
Characteristic
Symbol
Min
Max
Unit
SMALL–SIGNAL CHARACTERISTICS
Static Drain–Source “ON” Resistance
(VGS = 0, ID = 0, f = 1.0 kHz)
Input Capacitance
(VDS = 0, VGS = –12 Vdc, f = 1.0 MHz)
Reverse Transfer Capacitance
(VDS = 0, VGS = –12 Vdc, f = 1.0 MHz)
rds(on)
Ciss
Crss
—
—
—
100
10
4.0
Ohms
pF
pF
SWITCHING CHARACTERISTICS
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
VDD = 10 Vdc
Vdc,
VGS(on) = 0,
VGS(off) = –10 Vdc,
RG
′
= 50
Ω
ID(on) = 3.0 mAdc
ID(on) = 3.0 mAdc
ID(on) = 3.0 mAdc
ID(on) = 3.0 mAdc
td(on)
tr
td(off)
tf
—
—
—
—
8.0
10
15
30
ns
ns
ns
ns
Motorola Small–Signal Transistors, FETs and Diodes Device Data
4–131
2N5640
TYPICAL SWITCHING CHARACTERISTICS
1000
t d(on), TURN–ON DELAY TIME (ns)
500
200
100
50
20
10
5.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
50
RK = 0
RK = RD
′
1000
500
200
t r , RISE TIME (ns)
100
50
20
10
5.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
50
RK = 0
RK = RD
′
TJ = 25°C
VGS(off) = 12 V
TJ = 25°C
VGS(off) = 12 V
Figure 1. Turn–On Delay Time
Figure 2. Rise Time
1000
t d(off) , TURN–OFF DELAY TIME (ns)
500
200
RK = RD
′
t f , FALL TIME (ns)
100
50
20
10
5.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
50
RK = 0
TJ = 25°C
VGS(off) = 12 V
1000
500
200
100
50
20
10
5.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
50
RK = 0
RK = RD
′
TJ = 25°C
VGS(off) = 12 V
Figure 3. Turn–Off Delay Time
Figure 4. Fall Time
NOTE 1
+VDD
RD
SET VDS(off) = 10 V
INPUT
RGEN
50
Ω
50
Ω
VGEN
RK
RGG
VGG
RT
OUTPUT
50
Ω
INPUT PULSE
tr
≤
0.25 ns
tf
≤
0.5 ns
PULSE WIDTH = 2.0
µs
DUTY CYCLE
≤
2.0%
RGG
&
RK
RD
(R
)
50)
+
RRD
)
TRT
)
50
D
Figure 5. Switching Time Test Circuit
The switching characteristics shown above were measured using a
test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (–VGG). The
Drain–Source Voltage (VDS) is slightly lower than Drain Supply
Voltage (VDD) due to the voltage divider. Thus Reverse Transfer
Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to
VGG + VDS.
During the turn–on interval, Gate–Source Capacitance (C gs)
discharges through the series combination of RGen and RK. Cgd
must discharge to VDS(on) through RG and RK in series with the
parallel combination of effective load impedance (R′ D ) and
Drain–Source Resistance (rds). During the turn–off, this charge flow
is reversed.
Predicting turn–on time is somewhat difficult as the channel
resistance rds is a function of the gate–source voltage. While Cgs
discharges, VGS approaches zero and rds decreases. Since Cgd
discharges through rds, turn–on time is non–linear. During turn–off,
the situation is reversed with rds increasing as Cgd charges.
The above switching curves show two impedance conditions;
1) RK is equal to RD, which simulates the switching behavior of
cascaded stages where the driving source impedance is normally
the load impedance of the previous stage, and 2) RK = 0 (low
impedance) the driving source impedance is that of the generator.
4–132
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2N5640
y fs, FORWARD TRANSFER ADMITTANCE (mmhos)
20
15
10
10
7.0
5.0
Tchannel = 25°C
VDS = 15 V
C, CAPACITANCE (pF)
Cgs
7.0
5.0
Cgd
3.0
2.0
0.5 0.7
3.0
2.0
1.5
Tchannel = 25°C
(Cds IS NEGLIGIBLE)
1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
50
1.0
0.03 0.05 0.1
0.3 0.5
1.0
3.0 5.0
VR, REVERSE VOLTAGE (VOLTS)
10
30
Figure 6. Typical Forward Transfer Admittance
Figure 7. Typical Capacitance
200
rds(on), DRAIN–SOURCE ON–STATE
RESISTANCE (OHMS)
rds(on), DRAIN–SOURCE ON–STATE
RESISTANCE (NORMALIZED)
IDSS
= 10
160 mA
25
mA
50 mA
75 mA 100 mA
125 mA
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
– 70
– 40
20
50
80
110
Tchannel, CHANNEL TEMPERATURE (°C)
– 10
140
170
ID = 1.0 mA
VGS = 0
120
80
Tchannel = 25°C
40
0
0
1.0
2.0
3.0
4.0
5.0
6.0
VGS, GATE–SOURCE VOLTAGE (VOLTS)
7.0
8.0
Figure 8. Effect of Gate–Source Voltage
On Drain–Source Resistance
Figure 9. Effect of Temperature On
Drain–Source On–State Resistance
100
rds(on), DRAIN–SOURCE ON–STATE
RESISTANCE (OHMS)
90
80
70
60
50
40
30
20
10
9.0
8.0
VGS, GATE–SOURCE VOLTAGE (VOLTS)
Tchannel = 25°C
10
NOTE 2
The Zero–Gate–Voltage Drain Current (IDSS), is the principle
determinant of other J-FET characteristics. Figure 10 shows
the relationship of Gate–Source Off Voltage (VGS(off) and
Drain–Source On Resistance (rds(on)) to IDSS. Most of the
devices will be within
±10%
of the values shown in Figure 10.
This data will be useful in predicting the characteristic
variations for a given part number.
rDS(on) @ VGS = 0
VGS(off)
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
IDSS, ZERO–GATE–VOLTAGE DRAIN CURRENT (mA)
Figure 10. Effect of IDSS On Drain–Source
Resistance and Gate–Source Voltage
Motorola Small–Signal Transistors, FETs and Diodes Device Data
4–133
EMBOSSED TAPE AND REEL
SOT-23 and SOT-223 packages are available only in Tape and Reel.
Use the appropriate suffix indicated
below to order any of the SOT-23 and SOT-223 packages. (See Section 6 on Packaging for additional
information).
SOT-23:
available in 8 mm Tape and Reel
Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.
Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.
available in 12 mm Tape and Reel
Use the device title (which already includes the “T1” suffix) to order the 7 inch/1000 unit reel.
Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/4000 unit reel.
SOT-223:
RADIAL TAPE IN FAN FOLD BOX OR REEL
TO-92 packages are available in both bulk shipments and in Radial Tape in Fan Fold Boxes or Reels.
Fan Fold Boxes and Radial Tape Reel are the best methods for capturing devices for automatic insertion in
printed circuit boards.
TO-92:
available in Fan Fold Box
Add an “RLR” suffix and the appropriate Style code* to the device title to order the Fan Fold box.
available in 365 mm Radial Tape Reel
Add an “RLR” suffix and the appropriate Style code* to the device title to order the Radial Tape
Reel.
*Refer to Section 6 on Packaging for Style code characters and additional information on ordering
*requirements.
DEVICE MARKINGS/DATE CODE CHARACTERS
The SOT-23 package has a device marking and a date code etched on the device.
The generic
example below depicts both the device marking and a representation of the date code that appears on the
SOT-23 package.
ABC
D
The “D” represents a smaller alpha digit Date Code. The Date Code indicates the actual month in which the
part was manufactured.
4–2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
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