AT45DB321C-RL datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> storage> AT45DB321C-RL

AT45DB321C-RL: DescriptionFlash, 32MX1, PDSO28, 0.330 INCH, PLASTIC, SOIC-28; Categorystorage storage; File Size717KB，40 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

Download Datasheet Parametric View All

AT45DB321C-RL Overview

Flash, 32MX1, PDSO28, 0.330 INCH, PLASTIC, SOIC-28

AT45DB321C-RL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	SOIC
package instruction	SOP,
Contacts	28
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Other features	ORGANISED AS 8192 PAGES OF 528 BYTES EACH
Maximum clock frequency (fCLK)	40 MHz
JESD-30 code	R-PDSO-G28
JESD-609 code	e3
length	18.25 mm
memory density	33554432 bit
Memory IC Type	FLASH
memory width	1
Number of functions	1
Number of terminals	28
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX1
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	250
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	2.79 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	8.69 mm

Preview

Download Datasheet

View All

Features

•

Single 2.7 - 3.6V Supply

•

RapidS

™

Serial Interface: 40 MHz Maximum Clock Frequency

•

(SPI Modes 0 and 3 Compatible for Frequencies Up to 33 MHz)

Page Program

– 8192 Pages (528 Bytes/Page)

Automated Erase Operations

– Page Erase 528 Bytes

– Block Erase 4,224 Bytes

Two 528-byte SRAM Data Buffers – Allows Receiving of Data

while Reprogramming the Flash Array

Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

Low-power Dissipation

– 10 mA Active Read Current Typical

– 6 µA Standby Current Typical

Hardware and Software Data Protection Features

– Individual Sector Locking

Security: 128-byte Security Register

– 64-byte User Programmable Space

– Unique 64-byte Device Identifier

JEDEC Standard Manufacturer and Device ID Read

100,000 Program/Erase Cycles per Page Minimum

Data Retention – 20 years

Commercial and Industrial Temperature Ranges

Green (Pb/Halide-free/RoHS Compliant) Packaging Options

•

32-megabit

2.7 volt

DataFlash

AT45DB321C

For New

Designs Use

AT45DB321D

•

1. Description

The AT45DB321C is an SPI compatible, serial-interface Flash memory ideally suited

for a wide variety of digital voice-, image-, program code- and data-

storage applications. The AT45DB321C supports a 4-wire serial interface known as

RapidS for applications requiring very high speed operations.

Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In

addition to the 33-megabit main memory, the AT45DB321C also contains two SRAM

buffers of 528 bytes each.

The buffers allow the receiving of data while a page in the main page Memory is being

reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit

or byte alterability) is easily handled with a self-contained three step read-modify-write

operation. Unlike conventional Flash memories that are accessed randomly with mul-

tiple address lines and a parallel interface, the DataFlash uses a RapidS serial

interface to sequentially access its data. The simple sequential access dramatically

reduces active pin count, facilitates hardware layout, increases system reliability, min-

imizes switching noise, and reduces package size. The device is optimized for use in

many commercial and industrial applications where high-density, low-pin count, low-

voltage and low-power are essential. The device operates at clock frequencies up to

40 MHz with a typical active read current consumption of 10 mA.

3387M–DFLASH–2/08

5. Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions

and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with

the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main

memory address location. While the CS pin is low, toggling the SCK pin controls the loading of

the opcode and the desired buffer or main memory address location through the SI (serial input)

pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first.

Buffer addressing is referenced in the datasheet using the terminology BFA9-BFA0 to denote

the 10 address bits required to designate a byte address within a buffer. Main memory address-

ing is referenced using the terminology PA12-PA0 and BA9-BA0, where PA12-PA0 denotes the

13 address bits required to designate a page address and BA9-BA0 denotes the 10 address bits

required to designate a byte address within the page.

5.1

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either

one of the two SRAM data buffers. The DataFlash supports RapidS protocol for Mode 0 and

Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for

details on the clock cycle sequences for each mode.

5.1.1

Continuous Array Read

By supplying an initial starting address for the main memory array, the Continuous Array Read

command can be utilized to sequentially read a continuous stream of data from the device by

simply providing a clock signal; no additional addressing information or control signals need to

be provided. The DataFlash incorporates an internal address counter that will automatically

increment on every clock cycle, allowing one continuous read operation without the need of

additional address sequences. To perform a continuous read, an opcode of E8H must be

clocked into the device. The opcode is followed by three address bytes (which comprises 24-bit

page and byte address sequence) and 32 don’t care clock cycles. The first bit of the 24-bit

address sequence is reserved for upward and downward compatibility to larger and smaller den-

sity devices (see the notes under

Section 13.6 on page 25.

The next 13 bits (PA12-PA0) of the

24-bit address sequence specify which page of the main memory array to read, and the last

10 bits (BA9-BA0) of the 24-bit address sequence specify the starting byte address within the

page. The 32 don’t care clock cycles that follow the four address bytes are needed to initialize

the read operation. Following the don’t care clock cycles, additional clock pulses on the SCK pin

will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care

bytes, and the reading of data. When the end of a page in main memory is reached during a

Continuous Array Read, the device will continue reading at the beginning of the next page with

no delays incurred during the page boundary crossover (the crossover from the end of one page

to the beginning of the next page). When the last bit in the main memory array has been read,

the device will continue reading back at the beginning of the first page of memory. As with cross-

ing over page boundaries, no delays will be incurred when wrapping around from the end of the

array to the beginning of the array.

A low-to-high transition on the CS pin will terminate the read operation and tristate the output pin

(SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the

CAR

specification. The Continuous Array Read bypasses both data buffers and leaves the con-

tents of the buffers unchanged.

AT45DB321C

3387M–DFLASH–2/08

AT45DB321C

5.1.2

Main Memory Page Read

A main memory page read allows the user to read data directly from any one of the 8192 pages

in the main memory, bypassing both of the data buffers and leaving the contents of the buffers

unchanged. To start a page read, an opcode of D2H must be clocked into the device. The

opcode is followed by three address bytes (which comprise 24-bit page and byte address

sequence) and 32 don’t care clock cycles. The first bit of the 24-bit address sequence is a

reserved bit, the next 13 bits (PA12-PA0) of the 24-bit address sequence specify the page in

main memory to be read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify

the starting byte address within that page. The 32 don’t care clock cycles that follow the three

address bytes are sent to initialize the read operation. Following the don’t care bytes, additional

pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain

low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of

data. When the end of a page in main memory is reached, the device will continue reading back

at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read

operation and tristate the output pin (SO). The maximum SCK frequency allowable for the Main

Memory Page Read is defined by the f

SCK

specification. The Main Memory Page Read bypasses

both data buffers and leaves the contents of the buffers unchanged.

Buffer Read

Data can be read from either one of the two buffers, using different opcodes to specify which

buffer to read from. An opcode of D4H is used to read data from buffer 1, and an opcode of D6H

is used to read data from buffer 2. To perform a buffer read, the opcode must be clocked into the

device followed by three address bytes comprised of 14 don’t care bits and 10 buffer address

bits (BFA9-BFA0). Following the three address bytes, an additional don’t care byte must be

clocked in to initialize the read operation. Since the buffer size is 528 bytes, 10 buffer address

bits are required to specify the first byte of data to be read from the buffer. The CS pin must

remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the

reading of data. When the end of a buffer is reached, the device will continue reading back at the

beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation

and tristate the output pin (SO).

5.1.3

5.2

5.2.1

Program and Erase Commands

Buffer Write

Data can be clocked in from the SI pin into either buffer 1 or buffer 2. To load data into either

buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, fol-

lowed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9-

BFA0). The 10 buffer address bits specify the first byte in the buffer to be written. After the last

address byte has been clocked into the device, data can then be clocked in on subsequent clock

cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning

of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is

detected on the CS pin.

3387M–DFLASH–2/08

Recommended Resources

Single-junction transistor trigger circuit 2 that is not affected by power grid fluctuations

Infrared sensor faucet automatic handwasher circuit

Non-inductive switching regulated power supply circuit

Ultrasonic remote control stepless dimming light circuit.gif

LED slow charging circuit

2W audio amplifier

How to design a multi-channel and multi-range bipolar input signal acquisition system?: This system is: Input: >=4 signal range: multi-range such as +-0.1v, +-0.5v, +-60v Resolution: >=12bit Output: CAN bus sensor multi-level power supply: such as +-5v, +-10v, +-15v I am afraid that only...; hkey Embedded System

Fun little test! Let's start now....: [align=left][color=#000][/color][/align] [align=left][color=#000]Take out a blank sheet of paper. The answers will be at the end, so you can grade yourself. Give it a try! [/color][/align][align=left]...; maylove Analogue and Mixed Signal

I don't know if it's original, STM32 timer query delay: This part includes the basic configuration of the timer, then starts the timing, waits for the end of the timing through the interrupt flag, then clears the interrupt flag, and then turns off the time...; STM32F103 stm32/stm8

False triggering problem of high-sensitivity unidirectional thyristor: High-sensitivity unidirectional thyristor is connected in series with resistive load (because the control circuit can only provide weak trigger signal, only high-sensitivity unidirectional thyristor c...; harris Analog electronics

Simple and practical 51 software simulation platform: :) I'm asking for some coins from you all, original, simple and practical...; dcc024 stm32/stm8

Toss ULINK-ME (for learning only): I was free and tried the ULINK-ME on the STM32V100 board. I downgraded the firmware from V1.36 to V1.10. I was surprised to find that the computer prompted that new hardware was found, and it was ULIN...; cpx0102 stm32/stm8

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components