ICS8752BYT datasheet, PDF - EEWORLD Datasheet

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ICS8752BYT: DescriptionLow Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32; Categorylogic logic; File Size105KB，9 Pages; ManufacturerIDT (Integrated Device Technology)

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ICS8752BYT Overview

Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32

ICS8752BYT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LQFP,
Contacts	32
Reach Compliance Code	compliant

ICS8752BYT Preview

PRELIMINARY

Integrated

Circuit

Systems, Inc.

ICS8752

KEW

-8

LVCMOS C

LOCK

ULTIPLIER

ERO

ELAY

UFFER

EATURES

•

Fully integrated PLL

•

8 LVCMOS outputs, 7Ω typical output impedance

•

External feedback for ”zero delay” clock regeneration

•

Output frequency up to 240MHz

•

VCO range 220MHz to 480MHz

•

Dual LVCMOS clock inputs for redundant clock applications

•

LVCMOS control inputs

•

Bank skew, tsk(b), 100ps

•

Output skew, tsk(o), 150ps

•

Multiple-frequency skew, tsk(w), 200ps

•

Cycle-to-cycle jitter, tjit(cc), 100ps, typical

•

PLL reference zero delay, t(Ø), ±150ps, typical

•

Full 3.3V

•

32 lead low-profile QFP (LQFP)

•

7mm x 7mm x 1.4mm package body, 0.8mm lead pitch

•

0°C to 70°C ambient operating temperature

•

Functionally compatible with the MPC952 in some applications

ENERAL

ESCRIPTION

The ICS8752 is a low voltage, low skew clock

generator and a member of the HiPerClockS™

HiPerClockS™

family of High Performance Clock Solutions

from ICS. With output frequencies up to 240MHz

the ICS8752 is targeted for high performance

clock applications. Along with a fully integrated PLL the

ICS8752 contains frequency configurable outputs and an

external feedback input for regenerating clocks with “zero de-

lay”.

,&6

Dual clock inputs, REF_CLK1 and REF_CLK2, support

redundant clock applications. The CLK_SEL input determines

which reference clock is used. The output divider values of

Bank A and B are controlled by the DIV_SELA0:1, and

DIV_SELB0:1, respectively.

For test and system debug purposes the PLL_SEL input

allows the PLL to be bypassed. When HIGH the MR/nOE

input resets the internal dividers and forces the outputs to

the high impedance state.

The low impedance LVCMOS outputs of the ICS8752 are

designed to drive terminated transmission lines. The effec-

tive fanout of each output can be doubled by utilizing the

ability of each output to drive two series terminated trans-

mission lines.

LOCK

IAGRAM

PLL_SEL

PLL

FB_IN

REF_CLK1

REF_CLK2

CLK_SEL

DIV_SELA1

DIV_SELA0

PHASE

DETECTOR

VCO

÷2

÷4

÷6

÷8

÷12

SSIGNMENT

PLL_SEL

VDDO

VDDI

GND

QB3

QB2

32 31 30 29 28 27 26 25

QA0

QA1

QA2

QA3

DIV_SELB0

DIV_SELB1

DIV_SELA0

DIV_SELA1

MR/nOE

REF_CLK1

QB0

QB1

QB2

QB3

CLK_SEL

VDDA

VDDI

REF_CLK2

GND

QA0

QA1

VDDO

9 10 11 12 13 14 15 16

GND

QB1

QB0

VDDO

QA3

QA2

GND

ICS8752

GND

FB_IN

DIV_SELB1

DIV_SELB0

MR/nOE

32-Lead LQFP

Y package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

8752

www.icst.com/products/hiperclocks.html

REV. B MAY 4, 2001

PRELIMINARY

Integrated

Circuit

Systems, Inc.

ICS8752

KEW

-8

LVCMOS C

LOCK

ULTIPLIER

ERO

ELAY

UFFER

Type

Description

ABLE

1. P

ESCRIPTIONS

Number

1, 2

3, 4

7, 13

17, 24,

28, 29

11, 32

14, 15,

18, 19

16, 20,

21, 25

22, 23,

26, 27

Name

DIV_SELB0,

DIV_SELB1

DIV_SELA0,

DIV_SELA1

MR/nOE

REF_CLK1

GND

FB_IN

CLK_SEL

VDDA

VDDI

REF_CLK2

QA0, QA1,

QA2, QA3

VDDO

QB0, QB1,

QB2, QB3

PLL_SEL

VDDI

Input

Power

Input

Power

Input

Output

Power

Output

Unused

Input

Power

Pullup

Pulldown

Determines output divider values for bank B as described in Table 3.

LVCMOS / LVTTL interface levels.

Determines output divider values for bank A as described in Table 3.

Pulldown

LVCMOS / LVTTL interface levels.

When HIGH, resets dividers and forces output into high impedance state.

Pulldown

LVCMOS / LVTTL interface levels.

Pulldown Reference clock input. LVCMOS interface levels.

Ground pin. Connect to ground.

Feedback input to phase detector for regenerating clocks with "zero delay".

LVCMOS / LVTTL interface levels.

Selects between REF_CLK1 or REF_CLK2 as phase detector reference.

Pulldown When LOW selects REF_CLK1. When HIGH selects REF_CLK2.

LVCMOS / LVTTL interface levels.

PLL power supply pin. Connect to 3.3V.

Input and core power supply pin. Connect to 3.3V.

Pulldown Reference clock input. LVCMOS interface levels.

Bank A clock outputs.7Ω typical output impedance.

LVCMOS interface levels.

Output power supply pins. Connect to 3.3V.

Bank B clock outputs.7Ω typical output impedance.

LVCMOS interface levels.

Unused pin.

Selects between the PLL and the reference clock as the input to the

dividers. When HIGH select PLL. When LOW selects reference clock.

LVCMOS / LVTTL interface levels.

Input power supply pin. Connect to 3.3V.

Pulldown

8752

www.icst.com/products/hiperclocks.html

REV. B MAY 4, 2001

PRELIMINARY

Integrated

Circuit

Systems, Inc.

ICS8752

KEW

-8

LVCMOS C

LOCK

ULTIPLIER

ERO

ELAY

UFFER

Test Conditions

REF_CLK1,

REF_CLK2

PLL_SEL,

FB_IN,

CLK_SEL

DIV_SELA1,

DIV_SELA0,

DIV_SELB1,

DIV_SELB0

Minimum Typical

TBD

Maximum Units

ABLE

2. P

HARACTERISTICS

Symbol

Parameter

CIN

Input

Capacitance

TBD

RPULLUP

RPULLDOWN

CPD

ROUT

Input

Pullup Resistor

Input

Pulldown

Resistor

Power Dissipation

Capacitance

(per output)

Output

Impedance

KΩ

VDDA, VDDI, VDDO = 3.47V

TBD

Ω

ABLE

3. C

ONTROL

NPUTS

UNCTION

ABLE

Inputs

DIV_

SELA1

Outputs

DIV_

SELA0

DIV_

SELB1

DIV_

SELB0

QAx

Hi-Z

fVCO/2

fVCO/4

fVCO/6

fVCO/8

fREF_CLK1/2

fREF_CLK1/4

fREF_CLK1/6

fREF_CLK1/8

fREF_CLK2/2

fREF_CLK2/4

fREF_CLK2/6

fREF_CLK2/8

QBx

Hi-Z

fVCO/4

fVCO/6

fVCO/8

fVCO/12

fREF_CLK1/4

fREF_CLK1/6

fREF_CLK1/8

fREF_CLK1/12

fREF_CLK2/4

fREF_CLK2/6

fREF_CLK2/8

fREF_CLK2/12

MR/nOE

PLL_SEL

CLK_SEL

NOTE: For normal operation MR/nOE is LOW. When MR/nOE is HIGH all ouputs are disabled.

8752

www.icst.com/products/hiperclocks.html

REV. B MAY 4, 2001

PRELIMINARY

Integrated

Circuit

Systems, Inc.

ICS8752

KEW

-8

LVCMOS C

LOCK

ULTIPLIER

ERO

ELAY

UFFER

INPUTS

OUPUT

DIVIDER

MODE

REF_CLK1,

REF_CLK2

(MHz)

MIN

MAX

OUPUT

DIVIDER

MODE

÷2

÷4

÷6

÷8

÷2

÷4

÷6

÷8

÷2

÷4

÷6

÷8

÷2

÷4

÷6

÷8

OUTPUT

Multiplier

(NOTE 1)

0.667

0.5

1.5

0.75

1.33

1.5

ABLE

4A. QA O

UTPUT

REQUENCY W

/FB_IN = QB

FB_IN

DIV_SELB1

DIV_SELB0

DIV_SELA1

DIV_SELA0

÷4

62.5

125

÷6

41.67

83.33

÷8

31.25

62.5

20.83

41.67

NOTE 1: NOTE 1: VCO frequency range is 250MHz to 500MHz.

NOTE 2: QA output frequency equal to reference clock frequency times the multiplier ;

QB output frequency equal to reference clock.

8752

www.icst.com/products/hiperclocks.html

REV. B MAY 4, 2001

PRELIMINARY

Integrated

Circuit

Systems, Inc.

ICS8752

KEW

-8

LVCMOS C

LOCK

ULTIPLIER

ERO

ELAY

UFFER

INPUTS

REF_CLK1,

REF_CLK2

OUPUT

(MHz)

DIVIDER

MODE

MIN

MAX

OUTPUT

DIV_SELB1

DIV_SELB0

OUPUT

DIVIDER

MODE

÷4

÷6

÷8

÷4

÷6

÷8

÷4

÷6

÷8

÷4

÷6

÷8

Multiplier

(NOTE 2)

0.5

0.333

0.25

0.083

0.667

0.5

0.333

1.5

0.75

0.5

1.333

0.667

ABLE

4B. QB O

UTPUT

REQUENCY W

/FB_IN = QA

FB_IN

DIV_SELA1

DIV_SELA0

÷2

125

250

÷4

62.5

125

÷6

41.67

83.33

÷8

31.25

62.5

NOTE 1: VCO frequency range is 250MHz to 500MHz.

NOTE 2: QB output frequency equal to reference clock frequency times the multiplier ;

QA output frequency equal to reference clock.

ABLE

5. PLL I

NPUT

EFERENCE

HARACTERISTICS

VDDI=VDDA=3.3V±5%, T

=0°C

70°C

Symbol

fREF

tDC

Parameter

Input Reference Frequency

Input Rise Time

Input Fall Time

Input Reference Duty Cycle

Measured at 20% to 80% points

Measured at 20% to 80% point

TBD

Test Conditions

Minimum

Typical

Maximum

240

TBD

Units

MHz

8752

www.icst.com/products/hiperclocks.html

REV. B MAY 4, 2001

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

ICS8752BYT Related Products

	ICS8752BYT	ICS8752BY	ICS8752BYLF	ICS8752BYLFT
Description	Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32	Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32	Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32	Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32
Is it lead-free?	Contains lead	Contains lead	Lead free	Lead free
Is it Rohs certified?	incompatible	incompatible	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP	QFP	QFP
package instruction	LQFP,	LQFP,	7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32	7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32
Contacts	32	32	32	32
Reach Compliance Code	compliant	compliant	compliant	compliant
Input adjustment	-	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	-	S-PQFP-G32	S-PQFP-G32	S-PQFP-G32
JESD-609 code	-	e0	e3	e3
length	-	7 mm	7 mm	7 mm
Logic integrated circuit type	-	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	-	1	1	1
Number of terminals	-	32	32	32
Actual output times	-	8	8	8
Maximum operating temperature	-	70 °C	70 °C	70 °C
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	LQFP	LQFP	LQFP
Package shape	-	SQUARE	SQUARE	SQUARE
Package form	-	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	-	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	-	0.15 ns	0.15 ns	0.15 ns
Maximum seat height	-	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	-	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	-	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	-	3.3 V	3.3 V	3.3 V
surface mount	-	YES	YES	YES
technology	-	CMOS	CMOS	CMOS
Temperature level	-	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	-	TIN LEAD	MATTE TIN	MATTE TIN
Terminal form	-	GULL WING	GULL WING	GULL WING
Terminal pitch	-	0.8 mm	0.8 mm	0.8 mm
Terminal location	-	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	-	7 mm	7 mm	7 mm

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