HYS 72D256520GR-7/8-A
Low Profile Registered DDR-I SDRAM-Modules
2.5 V Low Profile 184-pin Registered DDR-I SDRAM Modules
2GByte Modules
PC1600 & PC2100
Preliminary Datasheet Rev. 0.9
• 184-pin Registered 8-Byte Dual-In-Line
DDR-I SDRAM Module for “1U” PC,
Workstation and Server main memory
applications
• Two bank 256M x 72 organization
• JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM) with a
single + 2.5 V (
±
0.2 V) power supply
• Built with DDR-I SDRAMs in 66-Lead TSOPII
package
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• Auto Refresh (CBR) and Self Refresh
• Performance:
-7
Component Speed Grade
Module Speed Grade
f
CK
f
CK
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register
and PLL devices.
• Serial Presence Detect with E
2
PROM
• Low Profile Modules form factor:
133.35 mm x 30,40 mm (1.2”) x 4.00 mm
(6,80 mm with stacked components)
• Based on Jedec standard reference card
layout RawCard “M”
• Gold plated contacts
-8
PC1600
125
100
Unit
DDR266A DDR200
PC2100
143
133
MHz
MHz
Clock Frequency (max.) @ CL = 2.5
Clock Frequency (max.) @ CL = 2
The HYS72Dxx5x0GR are low profile versions of the standard Registered DIMM modules with 1.2”
inch (30,40 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as
256M x 72 (2GB).
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications.
All control and address signals are re-driven on the DIMM using register devices and a PLL for the
clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the
SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs
feature serial presence detect based on a serial E
2
PROM device using the 2-pin I
2
C protocol. The
first 128 bytes are programmed with configuration data and the second 128 bytes are available to
the customer.
INFINEON Technologies
1
2002-05-08 (0.9)
HYS 72D256520GR-7/8-A
Registered DDR-I SDRAM-Modules
Ordering Information
Type
PC2100 (CL=2):
HYS 72D256520GR-7
PC1600 (CL=2):
HYS 72D256520GR-8
PC1600R-20220-N
two banks 2 GByte Reg. DIMM
512 MBit (x4)
(stacked)
1.2”
PC2100R-20330-N
two banks 2 GByte Reg. DIMM
512 MBit (x4)
(stacked)
1.2”
Compliance Code Description
SDRAM
Module
Technology height
Notes:
1. All part numbers end with a place code (not shown), designating the silicon-die revision. Reference information available
on request. Example: HYS 72D32500GR-8-A, indicating Rev.A die are used for SDRAM components.
2. The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100R”, the latencies (f.e.
“20330” means CAS latency = 2.5, trcd latency = 3 and trp latency =3 ) and the Raw Card used for this module
INFINEON Technologies
2
2002-05-08 (0.9)
HYS 72D256520GR-7/8-A
Registered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A11,A12
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
CAS
WE
CKE0, CKE1
DQS0 - DQS8
CK0, CK0
DM0 - DM8
DQS9 - DQS17
CS0 - CS1
Address Inputs
(A12 for 256Mb & 512Mb based modules)
V
DD
V
SS
V
DDQ
V
DDID
V
DDSPD
V
REF
SCL
SDA
SA0 - SA2
NC
DU
RESET
Power (+ 2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
Serial bus data line
slave address select
no connect
don’t use
Reset pin (forces register
inputs low) *)
Bank Selects
Data Input/Output
Check Bits (x72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
SDRAM low data strobes
Differential Clock Input
SDRAM low data mask/
high data strobes
Chip Selects
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the
Application Note at the end of this datasheet
Address Format
Density
2 GB
Organization
256M x 72
Memory
Banks
2
SDRAMs
(512Mb)
128M
×
4
# of
SDRAMs
36
(stacked)
# of row/bank/
columns bits
13/2/12
Refresh
8k
Period
64 ms
Interval
7.8
µ
s
INFINEON Technologies
3
2002-05-08 (0.9)
HYS 72D256520GR-7/8-A
Registered DDR-I SDRAM-Modules
Pin Configuration
PIN#
Symbol
PIN#
1
VREF
93
2
DQ0
94
3
VSS
95
4
DQ1
96
5
DQS0
97
6
DQ2
98
7
VDD
53
99
8
DQ3
54
100
9
NC
55
101
10
RESET
56
102
11
VSS
57
103
12
DQ8
58
104
13
DQ9
59
105
14
DQS1
60
106
15
VDDQ
61
107
16
DU
62
108
17
DU
63
109
18
VSS
64
110
19
DQ10
65
111
20
DQ11
66
112
21
CKE0
67
113
22
VDDQ
68
114
23
DQ16
69
115
24
DQ17
70
116
25
DQS2
71
117
26
VSS
72
118
27
A9
73
119
28
DQ18
74
120
29
A7
75
121
30
VDDQ
76
122
31
DQ19
77
123
32
A5
78
124
33
DQ24
79
125
34
VSS
80
126
35
DQ25
81
127
36
DQS3
82
128
37
A4
83
129
38
VDD
84
130
39
DQ26
85
131
40
DQ27
86
132
41
A2
87
133
42
VSS
88
134
43
A1
89
135
44
CB0
90
136
45
CB1
91
137
46
VDD
92
138
47
DQS8
139
Note: A12 is used for 256Mbit and 512Mbit based modules only
PIN#
48
49
50
51
52
Symbol
A0
CB2
VSS
CB3
BA1
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
DU
DU
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Symbol
VSS
DQ4
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC
DQ20
NC / A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Symbol
DM8/DQS17
A10
CB6
VDDQ
CB7
KEY
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
RAS
DQ45
VDDQ
CS0
CS1
DM5/DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
INFINEON Technologies
4
2002-05-08 (0.9)
HYS 72D256520GR-7/8-A
Registered DDR-I SDRAM-Modules
V SS
RS1
RS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D18
DM
DM0/DQS9
DQ4
DQ5
DQ6
DQ7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D27
DM
DQS1
CS
D1
DM
CS
D19
DM
DQ8
DQ9
DQ10
DQ11
DM1/DQS10
DQ12
DQ13
DQ14
DQ15
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D10
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D28
DM
DQS2
DQ16
DQ17
DQ18
DQ19
DM2/DQS11
CS
D2
DM
CS
D20
DM
DQ20
DQ21
DQ22
DQ23
CS
D11
DM
CS
D29
DM
DQS3
CS
D3
DM
CS
D21
DM
DQ24
DQ25
DQ26
DQ27
DM3/DQS12
CS
D12
DM
CS
D30
DM
DQ28
DQ29
DQ30
DQ31
DQS4
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D4
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D22
DM
DM4/DQS13
DQ36
DQ37
DQ38
DQ39
DM
CS
D13
DM
CS
D31
DM
DQS5
CS
D5
DM
CS
D23
DQ40
DQ41
DQ42
DQ43
DM5/DQS14
DQ44
DQ45
DQ46
DQ47
S
D14
S
D32
DM
DQS6
CS
D6
DM
CS
D24
DM
DQ48
DQ49
DQ50
DQ51
DM6/DQS15
DQ52
DQ53
DQ54
DQ55
CS
D15
CS
D33
DM
DQS7
CS
D7
DM
CS
D25
DM
DQ56
DQ57
DQ58
DQ59
DM7/DQS16
CS
D16
DQ60
DQ61
DQ62
DQ63
DM
DM
CS
D34
DM
DQS8
CS
D8
DM
CS
D26
CB0
CB1
CB2
CB3
DM8/DQS17
CB4
CB5
CB6
CB7
Serial PD
SDA
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D17
DM
CS
D35
DM
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
CS0
CS1
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
PC
K
PC
K
R
E
G
I
S
T
E
R
RS0 -> CS : SDRAMs D0-D17
RS1 -> CS : SDRAMs D18 -D35
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
RA0-RA12 -> A0-A12: SDRAMs D0 - D35
RRAS -> RAS : SDRAMs D0 - D35
RCAS -> CAS : SDRAMs D0 - D35
RCKE0 -> CKE: SDRAMs D0 - D17
RCKE1 -> CKE: SDRAMs D18 - D35
RWE -> WE : SDRAMs D0 - D35
RESET
SCL
V DDSPD
EEPROM
A0
A1
A2
VDD,VDDQ
VREF
V SS
D0 - D35
D0 - D35
D0 - D35
Strap: see Note 4
SA0 SA1 SA2
Notes:
V DDID
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: Two Bank 256M x 72 DDR-I SDRAM DIMM Modules (x4 comp.)
HYS72D256520GR on Raw Card N
INFINEON Technologies
5
2002-05-08 (0.9)