Features
•
Write Protect Pin for Hardware Data Protection
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•
•
•
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– Utilizes Different Array Protection Compared to the AT24C02A/04A
Medium-voltage and Standard-voltage Operation
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
Internally Organized 256 x 8 (2K), 512 x 8 (4K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400 kHz (2.7V, 5V) Clock Rate
8-byte Page (2K), 16-byte Page (4K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Lead-Free/Halogen-Free Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Two-wire
Automotive
Temperature
Serial
EEPROM
2K (256 x 8)
4K (512 x 8)
Description
The AT24C02A/04A provides 2048/4096 bits of serial electrically erasable and pro-
grammable read-only memory (EEPROM) organized as 256/512 words of 8 bits each.
The device is optimized for use in many automotive applications where low-power and
low-voltage operation are essential. The AT24C02A/04A is available in space-saving
8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a
two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to
5.5V) version.
AT24C02A
AT24C04A
Table 1.
Pin Configurations
Pin Name
A0–A2
SDA
SCL
WP
NC
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No-connect
A0
A1
A2
GND
A0
A1
A2
GND
8-lead
PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead
TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5083B–SEEPR–10/05
1
Absolute Maximum Ratings*
Operating Temperature......................................−40°C to +125°C
Storage Temperature
.........................................−65°C
to +150°C
Voltage on Any Pin
with Respect to Ground
........................................ −1.0V
to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Figure 1.
Block Diagram
START
STOP
LOGIC
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The A2, A1, and A0 pins are device
address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices
may be addressed on a single bus system. (Device addressing is discussed in detail
under
Device Addressing,
page 7).
The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four
4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
2
AT24C02A/04A
5083B–SEEPR–10/05
AT24C02A/04A
WRITE PROTECT (WP):
The AT24C02A/04A have a WP pin that provides hardware
data protection. The WP pin allows normal read/write operations when connected to
ground (GND). When the WP pin is connected to V
CC
, the write protection feature is
enabled and operates as shown. (See Table 1.)
Table 1.
Write Protect
Part of the Array Protected
WP Pin Status
At V
CC
At GND
24C02A
Upper Half (1K) Array
24C04A
Upper Half (2K) Array
Normal Read/Write Operations
Memory Organization
AT24C02A, 2K SERIAL EEPROM:
The 2K is internally organized with 32 pages of 8
bytes each. Random word addressing requires an 8-bit data word address.
AT24C04A, 4K SERIAL EEPROM:
The 4K is internally organized with 32 pages of 16
bytes each. Random word addressing requires a 9-bit data word address.
Table 2.
Pin Capacitance
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
cc
= +2.7V
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Table 3.
DC Characteristics
Applicable over recommended operating range from: T
A
=
−40°C
to +125°C, V
CC
= +2.7V to +5.5V
(unless otherwise noted)
Symbol
V
CC3
I
CC
I
CC
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Current V
CC
= 5.0V
Supply Current V
CC
= 5.0V
Standby Current V
CC
= 2.7V
Standby Current V
CC
= 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level V
CC
= 3.0V
Output Low Level V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
READ at 100 kHz
WRITE at 100 kHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
−0.6
V
CC
x 0.7
Test Condition
Min
2.7
0.4
2.0
1.6
8.0
0.10
0.05
Typ
Max
5.5
1.0
3.0
4.0
18.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
V
mA
mA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
3
5083B–SEEPR–10/05
Table 4.
AC Characteristics
Applicable over recommended operating range from T =
−40°C
to +125°C, V
CC
= +2.7V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted)
AT24C02A/04A
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(2)
Note:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(1)
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start
(2)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(2)
Inputs Fall Time
(2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
1M
0.6
50
5
0.1
1.2
0.6
0.6
0
100
300
300
1.2
0.6
50
0.9
Min
Max
400
Units
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
ms
Write Cycles
1. This parameter is characterized and is not 100% tested (T
A
= 25°C).
2. This parameter is characterized and is not 100% tested.
4
AT24C02A/04A
5083B–SEEPR–10/05
AT24C02A/04A
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 2). Data changes during SCL high periods will indicate a start or stop condition as
defined in Figure 2.
Figure 2.
Data Validity
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition
that must precede any other command (see Figure 3).
Figure 3.
Start and Stop Definition
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 3).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE:
The AT24C02A/04A features a low-power standby mode that is
enabled (a) upon power-up and (b) after the receipt of the STOP bit and the completion
of any internal operations.
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5083B–SEEPR–10/05
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