JANHCA2N6756 datasheet, PDF - EEWORLD Datasheet

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JANHCA2N6756: DescriptionPower Field-Effect Transistor, 14A I(D), 100V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, DIE-3; CategoryDiscrete semiconductor The transistor; File Size635KB，25 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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JANHCA2N6756 Overview

Power Field-Effect Transistor, 14A I(D), 100V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, DIE-3

JANHCA2N6756 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIE-3
Reach Compliance Code	compli
ECCN code	EAR99
Shell connection	DRAIN
Configuration	SINGLE
Minimum drain-source breakdown voltage	100 V
Maximum drain current (ID)	14 A
FET technology	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-XUUC-N3
JESD-609 code	e0
Number of components	1
Number of terminals	3
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	150 °C
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	UNCASED CHIP
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	N-CHANNEL
Maximum power dissipation(Abs)	75 W
Maximum pulsed drain current (IDM)	56 A
Certification status	Qualified
Guideline	MIL-19500/542G
surface mount	YES
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal location	UPPER
Maximum time at peak reflow temperature	NOT SPECIFIED
transistor applications	SWITCHING
Transistor component materials	SILICON
Base Number Matches	1

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The documentation and process conversion

measures necessary to comply with this revision

shall be completed by 22 December 2011.

INCH-POUND

MIL-PRF-19500/542J

22 September 2011

SUPERSEDING

MIL-PRF-19500/542H

26 April 2010

PERFORMANCE SPECIFICATION SHEET

SEMICONDUCTOR DEVICE, TRANSISTOR, FIELD EFFECT, N-CHANNEL,

SILICON, TYPES 2N6756, 2N6758, 2N6760, 2N6762,

JAN, JANTX, JANTXV, JANS, JANHC, AND JANKC

This specification is approved for use by all Departments

and Agencies of the Department of Defense.

The requirements for acquiring the product described herein shall consist of

this specification sheet and

MIL-PRF-19500.

1. SCOPE

1.1 Scope. This specification covers the performance requirements for N-channel, enhancement-mode, MOSFET,

power transistors. Four levels of product assurance are provided for each encapsulated device type as specified in

MIL-PRF-19500

and two levels of product assurance are provided for each unencapsulated device type.

1.2 Physical dimensions. See

figure 1

(TO-204AA; formerly TO-3),

figure 2,

and

for JANHC and JANKC die

dimensions. See

6.6

for unencapsulated device types.

1.3 Maximum ratings. Unless otherwise specified, T

= +25°C.

(1)

Type

+25°C

2N6756

2N6758

2N6760

2N6762

Type

(4)

A dc

2N6756

2N6758

2N6760

2N6762

14.0

9.0

5.5

4.5

A (pk)

°C

-55 to +150

+25°C

(free air)

= +25°C

V dc

100

200

400

500

V dc

100

200

400

500

ISO

100,000

feet

altitude

V dc

A dc

14.0

9.0

5.5

4.5

= +100°C

A dc

9.0

6.0

3.5

3.0

max

= +25°C

ohms

0.18

0.4

1.0

1.5

= +150°C

ohms

0.36

0.84

2.5

3.75

°C/W

1.67

(2) (3)

(2)

and T

STG

Max r

DS(on)

(1)

= 10 V dc, I

= I

400

500

See notes on next page.

* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,

ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to

Semiconductor@dla.mil.

Since contact

information can change, you may want to verify the currency of this address information using the ASSIST

Online database at

https://assist.daps.dla.mil/.

AMSC N/A

FSC 5961

MIL-PRF-19500/542J

2.2 Government documents.

2.2.1 Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a

part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are

those cited in the solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATIONS

MIL-PRF-19500

Semiconductor Devices, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-750

Test Methods for Semiconductor Devices.

(Copies of these documents are available online at

https://assist.daps.dla.mil/quicksearch/

https://assist.daps.dla.mil/

or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D,

Philadelphia, PA 19111-5094.)

2.3 Order of precedence. Unless otherwise noted herein or in the contract, in the event of a conflict between the

text of this document and the references cited herein, the text of this document takes precedence. Nothing in this

document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

3. REQUIREMENTS

3.1 General. The individual item requirements shall be as specified in

MIL-PRF-19500

and as modified herein.

3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a

manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)

before contract award (see

4.2

and

6.3).

3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as

specified in

MIL-PRF-19500.

nC ............................ nano coulomb.

............................ Rated avalanche current, non-repetitive.

3.4 Interface and physical dimensions. Interface and physical dimensions shall be as specified in

MIL-PRF-19500,

and on

figure 1

(TO-204AA; formerly TO-3),

figures 2,

and

for JANHC and JANKC die dimensions.

3.4.1 Lead finish. Lead finish shall be solderable in accordance with

MIL-PRF-19500, MIL-STD-750,

and herein.

Where a choice of lead finish is desired, it shall be specified in the acquisition document (see

6.2).

3.4.2 Internal construction. Multiple chip construction is not permitted to meet the requirements of this

specification.

3.5 Marking. Marking shall be in accordance with

MIL-PRF-19500.

JANHCA2N6756 Related Products

	JANHCA2N6756	JANHCA2N6758	JANHCA2N6760	JANTXV2N6760	JANTX2N6758	317-41-108-41-005000	JANTXV2N6758
Description	Power Field-Effect Transistor, 14A I(D), 100V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, DIE-3	Power Field-Effect Transistor, 9A I(D), 200V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, DIE-3	Power Field-Effect Transistor, 5.5A I(D), 400V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, DIE-3	Power Field-Effect Transistor, 5.5A I(D), 400V, 1.22ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-204AA, HERMETIC SEALED, MODIFIED TO-3, 2 PIN	Power Field-Effect Transistor, 9A I(D), 200V, 0.49ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-204AA, HERMETIC SEALED, MODIFIED TO-3, 2 PIN	Interconnect Socket Elevated Strip Socket	Power Field-Effect Transistor, 9A I(D), 200V, 0.49ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-204AA, HERMETIC SEALED, MODIFIED TO-3, 2 PIN
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	-	incompatible
package instruction	DIE-3	DIE-3	DIE-3	TO-3, 2 PIN	TO-3, 2 PIN	-	TO-3, 2 PIN
Reach Compliance Code	compli	compli	unknown	unknown	unknown	-	unknown
ECCN code	EAR99	EAR99	-	-	EAR99	-	EAR99
Shell connection	DRAIN	DRAIN	DRAIN	DRAIN	DRAIN	-	DRAIN
Configuration	SINGLE	SINGLE	SINGLE	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE	-	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	100 V	200 V	400 V	400 V	200 V	-	200 V
Maximum drain current (ID)	14 A	9 A	5.5 A	5.5 A	9 A	-	9 A
FET technology	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	-	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-XUUC-N3	R-XUUC-N3	R-XUUC-N3	O-MBFM-P2	O-MBFM-P2	-	O-MBFM-P2
JESD-609 code	e0	e0	e0	e0	e0	-	e0
Number of components	1	1	1	1	1	-	1
Number of terminals	3	3	3	2	2	-	2
Operating mode	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	-	ENHANCEMENT MODE
Maximum operating temperature	150 °C	150 °C	150 °C	150 °C	150 °C	-	150 °C
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	METAL	METAL	-	METAL
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	ROUND	ROUND	-	ROUND
Package form	UNCASED CHIP	UNCASED CHIP	UNCASED CHIP	FLANGE MOUNT	FLANGE MOUNT	-	FLANGE MOUNT
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
Polarity/channel type	N-CHANNEL	N-CHANNEL	N-CHANNEL	N-CHANNEL	N-CHANNEL	-	N-CHANNEL
Maximum power dissipation(Abs)	75 W	75 W	75 W	75 W	75 W	-	75 W
Maximum pulsed drain current (IDM)	56 A	36 A	22 A	22 A	36 A	-	36 A
Certification status	Qualified	Qualified	Qualified	Qualified	Qualified	-	Qualified
Guideline	MIL-19500/542G	MIL-19500/542G	MIL-19500/542G	MIL-19500/542	MIL-19500/542	-	MIL-19500/542
surface mount	YES	YES	YES	NO	NO	-	NO
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD	NO LEAD	NO LEAD	PIN/PEG	PIN/PEG	-	PIN/PEG
Terminal location	UPPER	UPPER	UPPER	BOTTOM	BOTTOM	-	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
transistor applications	SWITCHING	SWITCHING	SWITCHING	SWITCHING	SWITCHING	-	SWITCHING
Transistor component materials	SILICON	SILICON	SILICON	SILICON	SILICON	-	SILICON
Base Number Matches	1	1	1	1	1	-	-
Maximum drain current (Abs) (ID)	-	9 A	5.5 A	5.5 A	9 A	-	9 A
Maker	-	-	Infineon	Infineon	Infineon	-	Infineon

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