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IDT72605L35G

Description
Bi-Directional FIFO, 512X18, 21ns, Synchronous, CMOS, CPGA68, PGA-68
Categorystorage    storage   
File Size209KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT72605L35G Overview

Bi-Directional FIFO, 512X18, 21ns, Synchronous, CMOS, CPGA68, PGA-68

IDT72605L35G Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instructionPGA-68
Contacts68
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time21 ns
Other featuresBYPASS REGISTER
Maximum clock frequency (fCLK)28 MHz
period time35 ns
JESD-30 codeS-CPGA-P68
JESD-609 codee0
length29.464 mm
memory density9216 bit
Memory IC TypeBI-DIRECTIONAL FIFO
memory width18
Number of functions1
Number of terminals68
word count512 words
character code512
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512X18
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA68,11X11
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum standby current0.23 A
Maximum slew rate0.23 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width29.464 mm
CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
Integrated Device Technology, Inc.
IDT72605
IDT72615
FEATURES:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 x 2 organization (IDT 72605)
• 512 x 18 x 2 organization (IDT 72615)
• Synchronous interface for fast (20ns) read and write
cycle times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-
power bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFO™ is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individ-
ual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memo-
ries. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed,
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
D
A0
-D
A17
R/
W
A
EN
A
OE
A
HIGH
Z
CONTROL
CLK
A
INPUT REGISTER
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
MUX
MEMORY
ARRAY
512 x 18
256 x 18
RESET
LOGIC
CS
A
A
2
A
1
A
0
µ
P
INTERFACE
FLAG
LOGIC
RS
EF
BA
PAE
BA
PAF
BA
FF
BA
3
7
EF
AB
PAE
AB
PAF
AB
FF
AB
FLAG
LOGIC
POWER
SUPPLY
INPUT REGISTER
V
CC
GND
CLK
B
OUTPUT REGISTER
HIGH
Z
CONTROL
OE
B
R/
W
B
EN
B
BYP
B
COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
D
B0
-D
B17
2704 drw 01
SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
DECEMBER 1996
DSC-2704/5
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
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