R1QNA4418RBG-30IB0 datasheet, PDF

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R1QNA4418RBG-30IB0: Description144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency); File Size907KB，30 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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R1QNA4418RBG-30IB0 Overview

144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

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Datasheet

R1QNA4436RBG,R1QNA4418RBG

144-Mbit QDR™II+ SRAM 2-word Burst

Architecture (2.0 Cycle Read latency)

Description

The R1QNA4436RBG is a 4,194,304-word by 36-bit and the R1QNA4418RBG is a 8,388,608-word by 18-bit

synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are

controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are

suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit

configuration. These products are packaged in 165-pin plastic FBGA package.

R10DS0148EJ0200

Rev.2.00

Aug 01, 2014

Features

Power Supply

1.8 V for core (V

), 1.4 V to V

for I/O (V

DDQ

)

Clock

Fast clock cycle time for high bandwidth

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems

Clock-stop capability with

μs

restart

I/O

Separate independent read and write data ports with concurrent transactions

100% bus utilization DDR read and write operation

HSTL I/O

User programmable output impedance

PLL circuitry for wide output data valid window and future frequency scaling

Data valid pin (QVLD) to indicate valid data on the output

Function

Two-tick burst for low DDR transaction size

Internally self-timed write control

Simple control logic for easy depth expansion

JTAG 1149.1 compatible test access port

Package

165 FBGA package (15 x 17 x 1.4 mm)

R10DS0148EJ0200 Rev.2.00

Aug 01, 2014

Page 1 of 29

R1QNA4418RBG-30IB0 Related Products

	R1QNA4418RBG-30IB0	R1QNA4418RBG-30IA0	R1QNA4436RBG-30IB0	R1QNA4436RBG-33IA0	R1QNA4418RBG-33IA0	R1QNA4418RBG-33IB0	R1QNA4436RBG-30IA0	R1QNA4436RBG-33IB0	R1QNA4436RBG_15
Description	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)	144-Mbit QDRâ¢II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

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