W28J800TT90L datasheet, PDF - EEWORLD Datasheet

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W28J800TT90L: DescriptionFlash, 512KX16, 90ns, PDSO48, 12 X 20 MM, TSOP-48; Categorystorage storage; File Size3MB，49 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W28J800TT90L Overview

Flash, 512KX16, 90ns, PDSO48, 12 X 20 MM, TSOP-48

W28J800TT90L Parametric

Parameter Name	Attribute value
Maker	Winbond Electronics Corporation
Parts packaging code	TSOP
package instruction	TSOP1, TSSOP48,.8,20
Contacts	48
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	90 ns
Other features	TOP BOOT BLOCK
Spare memory width	8
startup block	TOP
command user interface	YES
Data polling	NO
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	18.4 mm
memory density	8388608 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	8,15
Number of terminals	48
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	8K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
switch bit	NO
type	NOR TYPE
width	12 mm

W28J800TT90L Preview

Preliminary W28J800B/T

8M(512K

16/1M

BOOT BLOCK FLASH MEMORY

Table of Contents-

1. GENERAL DESCRIPTION ..................................................................................................................3

2. FEATURES ..........................................................................................................................................3

3. PRODUCT OVERVIEW .......................................................................................................................4

4. BLOCK DIAGRAM ...............................................................................................................................5

Block Organization............................................................................................................................5

5. PIN CONFIGURATION........................................................................................................................6

6. PIN DESCRIPTION..............................................................................................................................7

7. PRINCIPLES OF OPERATION............................................................................................................8

Data Protection .................................................................................................................................8

8. BUS OPERATION..............................................................................................................................10

Read ...............................................................................................................................................10

Output Disable ................................................................................................................................10

Standby ...........................................................................................................................................10

Reset...............................................................................................................................................10

Read Identifier Codes .....................................................................................................................11

OTP (One Time Program) Block ....................................................................................................12

Write ...............................................................................................................................................12

9. COMMAND DEFINITIONS ................................................................................................................13

Read Array Command ....................................................................................................................15

Read Identifier Codes Command ...................................................................................................15

Read Status Register Command ....................................................................................................15

Clear Status Register Command ....................................................................................................16

Block Erase Command ...................................................................................................................16

Full Chip Erase Command..............................................................................................................16

Word/Byte Write Command............................................................................................................17

Block Erase Suspend Command....................................................................................................17

Word/Byte Write Suspend Command ............................................................................................18

Set Block and Permanent Lock-bit Commands..............................................................................18

Clear Block Lock-bits Command ....................................................................................................19

OTP Program Command................................................................................................................20

Block Locking by the #WP ..............................................................................................................20

Publication Release Date: May 21, 2002

Revision A1

-1-

Preliminary W28J800B/T

10. DESIGN CONSIDERATIONS ..........................................................................................................31

Three-line Output Control ...............................................................................................................31

RY/#BY and WSM Polling...............................................................................................................31

Power Supply Decoupling ...............................................................................................................31

Trace on Printed Circuit Boards ..............................................................................................31

, V

, #RESET Transitions ......................................................................................................31

Power-up/Down Protection .............................................................................................................32

Power Dissipation ...........................................................................................................................32

Data Protection Method ..................................................................................................................32

11. ELECTRICAL SPECIFICATIONS ....................................................................................................33

Absolute Maximum Ratings*...........................................................................................................33

Operating Conditions ......................................................................................................................33

Capacitance(1)................................................................................................................................34

AC Input/Output Test Conditions ....................................................................................................34

DC Characteristics..........................................................................................................................35

AC Characteristics - Read-only Operations(1) ...............................................................................37

AC Characteristics - Write Operations(1) .......................................................................................40

Reset Operations ............................................................................................................................44

Block Erase, Full Chip Erase, Word/Byte Write And Lock-Bit Configuration Performance(3) .......45

12. ADDITIONAL INFORMATION .........................................................................................................46

Recommended Operating Conditions.............................................................................................46

13. ORDERING INFORMATION ...........................................................................................................48

14. PACKAGE DIMENSION ..................................................................................................................48

15. VERSION HISTORY ........................................................................................................................49

-2-

Preliminary W28J800B/T

1. GENERAL DESCRIPTION

The product is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of

applications. The product can operate at V

= 2.7V

−

3.6V and V

= 2.7V

−

3.6V or 11.7V

−

12.3V.

Its low voltage operation capability realize battery life and suits for cellular phone application. Its Boot,

Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible

component suitable for portable terminals and personal computers. Its enhanced suspend capabilities

provide for an ideal solution for code + data storage applications. For secure code storage

applications, such as networking, where code is either directly executed out of flash or downloaded to

DRAM, the product offers four levels of protection: absolute protection with V

≤

PPLK

, selective

hardware block locking or flexible software block locking. These alternatives give designers ultimate

control of their code security needs. The product is manufactured on 0.25

µm

process technology. It

come in industry-standard package: the 48-lead TSOP, ideal for board constrained applications.

2. FEATURES

•

Low Voltage Operation

−

= V

= 2.7V

−

3.6V Single Voltage

OTP (One Time Program) Block

−

3963 word + 4 word Program only array

User-Configurable x 8 or x 16 Operation

High-Performance Read Access Time

−

90 nS (V

= 2.7V

−

3.6V)

Operating Temperature

−

0° C to +70° C (W28J800BT/TT90C)

−

-40° C to +85° C (W28J800BT/TT90L)

Low Power Management

−

Typ. 2

µA

= 3.0V) Standby Current

−

Automatic Power Savings Mode Decreases

ICCR in Static Mode

−

Typ. 120

µA

= 3.0V, T

= +25° C,

f = 32 KHz) Read Current

•

−

Word/Byte Write Suspend to Read

−

Block Erase Suspend to Word/Byte Write

−

Block Erase Suspend to Read

Enhanced Data Protection Features

−

Absolute Protection with V

≤

PPLK

−

Block Erase, Full Chip Erase, Word/Byte

Write and Lock-Bit Configuration Lockout

during Power Transitions

−

Block Locking with Command and #WP

−

Permanent Locking

Automated Block Erase, Full Chip Erase, Low

Power Management Word/Byte Write and

Lock-Bit Configuration

−

Command User Interface (CUI)

−

Status Register (SR)

•

Optimized Array Blocking Architecture

−

Two 4K-word (8K-byte) Boot Blocks

−

Six 4K-word (8K-byte) Parameter Blocks

−

Fifteen 32K-word (64K-byte) Main Blocks

−

Top or Bottom Boot Location

•

Extended Cycling Capability

−

Minimum 100,000 Block Erase Cycles

•

Low power consumption

−

Active current: 20 mA (typ.)

−

Standby current: 15

µA

(typ.)

•

SRAM-Compatible Write Interface

•

Industry-Standard Packaging

−

48-Lead TSOP

•

Nonvolatile Flash Technology

•

CMOS Process (P-type silicon substrate)

•

Not designed or rated as radiation hardened

•

Enhanced Automated Suspend Options

-3-

Publication Release Date: May 21, 2002

Revision A1

Preliminary W28J800B/T

3. PRODUCT OVERVIEW

The product is a high-performance 8M-bit Boot Block Flash memory organized as 512K-word of 16 bits

or 1Mbyte of 8 bits. The 512K-word/1M-byte of data is arranged in two 4K-word/8K-byte boot blocks,

six 4K-word/8Kbyte parameter blocks and fifteen 32K-word/64K-byte main blocks which are individually

erasable, lockable and unlockable in-system. The memory map is shown in Figure 3.

The dedicated V

pin gives complete data protection when V

≤

PPLK

A Command User Interface (CUI) serves as the interface between the system processor and internal

operation of the device. A valid command sequence written to the CUI initiates device automation. An

internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for

block erase, full chip erase, word/byte write and lock-bit configuration operations.

A block erase operation erases one of the device’s 32Kword/64K-byte blocks typically within 1.2S (3V

, 3V V

), 4K-word/8K-byte blocks typically within 0.6s (3V V

, 3V V

) independent of other

blocks. Each block can be independently erased minimum 100,000 times. Block erase suspend mode

allows system software to suspend block erase to read or write data from any other block.

Writing memory data is performed in word/byte increments of the device’s 32K-word blocks typically

within 33

µS

(3V V

, 3V V

), 64K-byte blocks typically within 31µS (3V V

, 3V V

), 4K-word

blocks typically within 36

µS

(3V V

, 3V V

), 8Kbyte blocks typically within 32

µS

(3V V

, 3V V

Word/byte write suspend mode enables the system to read data or execute code from any other flash

memory array location.

Individual block locking uses a combination of bits, thirty-nine block lock-bits, a permanent lock-bit and

#WP pin, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word/byte

write operations, while the permanent lock-bit gates block lock-bit modification and locked block

alternation. Lock-bit configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear

Block Lock-Bits commands) set and cleared lock-bits.

The status register indicates when the WSM’s block erase, full chip erase, word/byte write or lock-bit

configuration operation is finished.

The RY/#BY output gives an additional indicator of WSM activity by providing both a hardware signal of

status (versus software polling) and status masking (interrupt masking for background block erase, for

example). Status polling using RY/#BY minimizes both CPU overhead and system power consumption.

When low, RY/#BY indicates that the WSM is performing a block erase, full chip erase, word/byte write

or lock-bit configuration. RY/#BY-high Z indicates that the WSM is ready for a new command, block

erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in

reset mode.

The access time is 90 nS (tAVQV) over the operating temperature range and V

supply voltage range

of 2.7V

−

3.6V.

The Automatic Power Savings (APS) feature substantially reduces active current when the device is in

static mode (addresses not switching). In APS mode, the typical ICCR current is 2

µA

(CMOS) at 3.0V

When #CE and #RESET pins are at V

, the ICC CMOS standby mode is enabled. When the

#RESET pin is at Vss, reset mode is enabled which minimizes power consumption and provides write

protection. A reset time (tPHQV) is required from #RESET switching high until outputs are valid.

Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the CUI are

recognized. With #RESET at Vss, the WSM is reset and the status register is cleared.

-4-

Preliminary W28J800B/T

Please do not execute reprogramming "0" for the bit which has already been programed "0". Overwrite

operation may generate inerasable bit. In case of reprogramming "0" to the data which has been

programmed "1".

•

Program "0" for the bit in which you want to change data from "1" to "0".

Program "1" for the bit which has already been programmed "0".

For example, changing data from "10111101" to "10111100" requires "11111110" programming.

4. BLOCK DIAGRAM

Figure 1. Block Diagram

Block Organization

This product features an asymmetrically-blocked architecture providing system memory integration.

Each erase block can be erased independently of the others up to 100,000 times. For the address

locations of the blocks, see the memory map in Figure 3.

-5-

Publication Release Date: May 21, 2002

Revision A1

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