W180-51GT datasheet, PDF - EEWORLD Datasheet

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W180-51GT: DescriptionClock Generator, 28MHz, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8; CategoryThe embedded processor and controller Microcontrollers and processors; File Size122KB，9 Pages; ManufacturerCypress Semiconductor

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W180-51GT Overview

Clock Generator, 28MHz, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8

W180-51GT Parametric

Parameter Name	Attribute value
Maker	Cypress Semiconductor
Parts packaging code	SOIC
package instruction	SOP,
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	ALSO OPERATES AT 5V SUPPLY
JESD-30 code	R-PDSO-G8
length	4.889 mm
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	28 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Master clock/crystal nominal frequency	28 MHz
Certification status	Not Qualified
Maximum seat height	1.727 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.8985 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

W180-51GT Preview

W180

Peak Reducing EMI Solution

Features

•

Cypress PREMIS™ family offering

• Generates an EMI optimized clocking signal at the

output

• Selectable output frequency range

• Single 1.25% or 3.75% down or center spread output

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low power CMOS design

• Available in 8-pin SOIC (Small Outline Integrated

Circuit)

Table 1. Modulation Width Selection

SS%

W180-01, 02, 03

Output

≥

out

≥

–

1.25%

≥

out

≥

–

3.75%

W180-51, 52, 53

Output

+ 0.625%

≥

–

0.625%

+ 1.875%

≥

–1.875%

Table 2. Frequency Range Selection

W180 Option#

FS2

FS1

-01, 51

(MHz)

≤

-02, 52

(MHz)

≤

N/A

-03, 53

(MHz)

N/A

≤

Key Specifications

Supply Voltages: ...........................................V

= 3.3V±5%

or V

= 5V±10%

Frequency Range: .............................. 8 MHz

≤

28 MHz

Cycle to Cycle Jitter: ....................................... 300 ps (max.)

Selectable Spread Percentage: ....................1.25% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output Rise and Fall Time: .................................. 5 ns (max.)

Simplified Block Diagram

3.3V or 5.0V

Pin Configurations

SOIC

W180-01/51

XTAL

Input

CLKIN or X1

NC or X2

GND

SS%

FS2

FS1

VDD

CLKOUT

W180

Spread Spectrum

Output

(EMI suppressed)

W180-02/03

W180-52/53

CLKIN or X1

NC or X2

GND

SS%

SSON#

FS1

VDD

CLKOUT

3.3V or 5.0V

Oscillator or

Reference Input

W180

Spread Spectrum

Output

(EMI suppressed)

PREMIS is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

Document #: 38-07156 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised September 25, 2001

W180

Pin Definitions

Pin Name

CLKOUT

CLKIN or X1

Pin No.

Type

Pin Description

Output Modulated Frequency:

Frequency modulated copy of the unmodu-

lated input clock (SSON# asserted).

Crystal Connection or External Reference Frequency Input:

This pin has

dual functions. It may either be connected to an external crystal, or to an

external reference clock.

Crystal Connection:

Input connection for an external crystal. If using an ex-

ternal reference, this pin must be left unconnected.

Spread Spectrum Control (Active LOW):

Asserting this signal (active LOW)

turns the internal modulation waveform on. This pin has an internal pull-down

resistor.

Frequency Selection Bit(s) 1 and 2:

These pins select the frequency range

of operation. Refer to

Table 2.

These pins have internal pull-up resistors.

Modulation Width Selection:

When Spread Spectrum feature is turned on,

this pin is used to select the amount of variation and peak EMI reduction that

is desired on the output signal. Internal pull-up resistor.

Power Connection:

Connected to 3.3V or 5V power supply.

Ground Connection:

This should be connected to the common ground plane.

NC or X2

SSON#

8 (-02, -03

52, 53)

7, 8 (-01, 51)

FS1:2

SS%

VDD

GND

Document #: 38-07156 Rev. *A

Page 2 of 9

W180

Overview

The W180 products are one series of devices in the Cypress

PREMIS family. The PREMIS family incorporates the latest

advances in PLL spread spectrum frequency synthesizer tech-

niques. By frequency modulating the output with a low-fre-

quency carrier, peak EMI is greatly reduced. Use of this tech-

nology allows systems to pass increasingly difficult EMI testing

without resorting to costly shielding or redesign.

In a system, not only is EMI reduced in the various clock lines,

but also in all signals which are synchronized to the clock.

Therefore, the benefits of using this technology increase with

the number of address and data lines in the system. The Sim-

plified Block Diagram on page 1 shows a simple implementa-

tion.

input. The output frequency is then equal to the ratio of P/Q

times the reference frequency. (Note: For the W180 the output

frequency is equal to the input frequency.) The unique feature

of the Spread Spectrum Frequency Timing Generator is that a

modulating waveform is superimposed at the input to the VCO.

This causes the VCO output to be slowly swept across a pre-

determined frequency band.

Because the modulating frequency is typically 1000 times

slower than the fundamental clock, the spread spectrum pro-

cess has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI re-

duction depends on the shape, modulation percentage, and

frequency of the modulating waveform. While the shape and

frequency of the modulating waveform are fixed for a given

frequency, the modulation percentage may be varied.

Using frequency select bits (FS2:1 pins), the frequency range

can be set (see

Table 2).

Spreading percentage is set with pin

SS% as shown in

Table 1.

A larger spreading percentage improves EMI reduction. How-

ever, large spread percentages may either exceed system

maximum frequency ratings or lower the average frequency to

a point where performance is affected. For these reasons,

spreading percentages options are provided.

Functional Description

The W180 uses a phase-locked loop (PLL) to frequency mod-

ulate an input clock. The result is an output clock whose fre-

quency is slowly swept over a narrow band near the input sig-

nal. The basic circuit topology is shown in

Figure 1.

The input

reference signal is divided by Q and fed to the phase detector.

A signal from the VCO is divided by P and fed back to the

phase detector also. The PLL will force the frequency of the

VCO output signal to change until the divided output signal

and the divided reference signal match at the phase detector

Clock Input

Freq.

Divider

Phase

Detector

Charge

Pump

Reference Input

VCO

Post

Dividers

CLKOUT

(EMI suppressed)

Modulating

Waveform

Feedback

Divider

PLL

GND

Figure 1. Functional Block Diagram

Document #: 38-07156 Rev. *A

Page 3 of 9

W180

Spread Spectrum Frequency Timing

Generation

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the am-

plitudes of the radiated electromagnetic emissions are re-

duced. This effect is depicted in

Figure 2.

As shown in

Figure 2,

a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is:

dB = 6.5 + 9*log

(P) + 9*log

(F)

Where

is the percentage of deviation and

is the frequency

in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in

Figure 3.

This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions.

Figure

details the Cypress spreading pattern. Cypress does offer

options with more spread and greater EMI reduction. Contact

your local Sales representative for details on these devices.

EMI Reduction

SSFTG

Typical Clock

Amplitude (dB)

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Frequency Span (MHz)

Center Spread

Frequency Span (MHz)

Down Spread

Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX.

FREQUENCY

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

MIN.

Figure 3. Typical Modulation Profile

Document #: 38-07156 Rev. *A

100%

Page 4 of 9

W180

Absolute Maximum Ratings

[1]

Stresses greater than those listed in this table may cause per-

manent damage to the device. These represent a stress rating

only. Operation of the device at these or any other conditions

above those specified in the operating sections of this specifi-

cation is not implied. Maximum conditions for extended peri-

ods may affect reliability.

Rating

–0.5 to +7.0

–65 to +150

0 to +70

–55 to +125

0.5

Unit

°C

Parameter

, V

STG

Description

Voltage on any pin with respect to GND

Storage Temperature

Operating Temperature

Ambient Temperature under Bias

Power Dissipation

DC Electrical Characteristics

0°C < T

< 70°C, V

= 3.3V ±5%

Parameter

OUT

Description

Supply Current

Power Up Time

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

Input High Current

Output Low Current

Output High Current

Input Capacitance

Input Pull-Up Resistor

Clock Output Impedance

500

Note 2

@ 0.4V, V

= 3.3V

@ 2.4V, V

= 3.3V

2.4

–50

2.4

0.4

First locked clock cycle after Power

Good

Test Condition

Min.

Typ.

Max.

0.8

Unit

µA

kΩ

Ω

Note:

Single Power Supply:

The voltage on any input or I/O pin cannto exceed the power pin during power-up.

2. Inputs FS2:1& SS% have a pull-up resistor; Input SSON# has a pull-down resistor.

Document #: 38-07156 Rev. *A

Page 5 of 9

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Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	SOP,	SOP,	SOP,	0.150 INCH, PLASTIC, SOIC-8	SOP,	SOP,	0.150 INCH, PLASTIC, SOIC-8	SOP,	0.150 INCH, PLASTIC, SOIC-8
Contacts	8	8	8	8	8	8	8	8	8
Reach Compliance Code	unknown	unknown	unknown	not_compliant	unknown	unknown	not_compliant	unknown	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY
JESD-30 code	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
length	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm
Number of terminals	8	8	8	8	8	8	8	8	8
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Maximum output clock frequency	28 MHz	28 MHz	28 MHz	15 MHz	15 MHz	28 MHz	15 MHz	15 MHz	28 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP	SOP	SOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Master clock/crystal nominal frequency	28 MHz	28 MHz	28 MHz	15 MHz	15 MHz	28 MHz	15 MHz	15 MHz	28 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm
Maximum supply voltage	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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