DPLD910-25 datasheet, PDF - EEWORLD Datasheet

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DPLD910-25: DescriptionUV PLD, 28ns, PAL-Type, CMOS, CDIP40, WINDOWED, CERDIP-40; CategoryProgrammable logic devices Programmable logic; File Size649KB，22 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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DPLD910-25 Overview

UV PLD, 28ns, PAL-Type, CMOS, CDIP40, WINDOWED, CERDIP-40

DPLD910-25 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	DIP
package instruction	WDIP, DIP40,.6
Contacts	40
Reach Compliance Code	compliant
Other features	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Architecture	PAL-TYPE
maximum clock frequency	27.7 MHz
JESD-30 code	R-GDIP-T40
JESD-609 code	e0
length	52.325 mm
Dedicated input times	12
Number of I/O lines	24
Number of entries	36
Output times	24
Number of product terms	240
Number of terminals	40
Maximum operating temperature	70 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	WDIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE, WINDOW
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	UV PLD
propagation delay	28 ns
Certification status	Not Qualified
Maximum seat height	5.72 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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	DPLD910-25	PPLD910-25	PPLD910-15	DPLD910-12	DPLD910-15	PPLD910-12	NPLD910-25	NPLD910-15
Description	UV PLD, 28ns, PAL-Type, CMOS, CDIP40, WINDOWED, CERDIP-40	OT PLD, 28ns, PAL-Type, CMOS, PDIP40, PLASTIC, DIP-40	OT PLD, 18ns, PAL-Type, CMOS, PDIP40, PLASTIC, DIP-40	UV PLD, 15ns, PAL-Type, CMOS, CDIP40, WINDOWED, CERDIP-40	UV PLD, 18ns, PAL-Type, CMOS, CDIP40, WINDOWED, CERDIP-40	OT PLD, 15ns, PAL-Type, CMOS, PDIP40, PLASTIC, DIP-40	OT PLD, 28ns, PAL-Type, CMOS, PQCC44, PLASTIC, LCC-44	OT PLD, 18ns, PAL-Type, CMOS, PQCC44, PLASTIC, LCC-44
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Intel	Intel	Intel	Intel	Intel	Intel	Intel	Intel
Parts packaging code	DIP	DIP	DIP	DIP	DIP	DIP	LCC	LCC
package instruction	WDIP, DIP40,.6	DIP, DIP40,.6	DIP, DIP40,.6	WDIP, DIP40,.6	WDIP, DIP40,.6	DIP, DIP40,.6	QCCJ, LDCC44,.7SQ	QCCJ, LDCC44,.7SQ
Contacts	40	40	40	40	40	40	44	44
Reach Compliance Code	compliant	unknown	compliant	compliant	compliant	compliant	unknown	compliant
Other features	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Architecture	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE
maximum clock frequency	27.7 MHz	27.7 MHz	45.4 MHz	52.6 MHz	45.4 MHz	52.6 MHz	27.7 MHz	45.4 MHz
JESD-30 code	R-GDIP-T40	R-PDIP-T40	R-PDIP-T40	R-GDIP-T40	R-GDIP-T40	R-PDIP-T40	S-PQCC-J44	S-PQCC-J44
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	52.325 mm	52.26 mm	52.26 mm	52.325 mm	52.325 mm	52.26 mm	16.5862 mm	16.5862 mm
Dedicated input times	12	12	12	12	12	12	12	12
Number of I/O lines	24	24	24	24	24	24	24	24
Number of entries	36	36	36	36	36	36	36	36
Output times	24	24	24	24	24	24	24	24
Number of product terms	240	240	240	240	240	240	240	240
Number of terminals	40	40	40	40	40	40	44	44
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	WDIP	DIP	DIP	WDIP	WDIP	DIP	QCCJ	QCCJ
Encapsulate equivalent code	DIP40,.6	DIP40,.6	DIP40,.6	DIP40,.6	DIP40,.6	DIP40,.6	LDCC44,.7SQ	LDCC44,.7SQ
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE
Package form	IN-LINE, WINDOW	IN-LINE	IN-LINE	IN-LINE, WINDOW	IN-LINE, WINDOW	IN-LINE	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Programmable logic type	UV PLD	OT PLD	OT PLD	UV PLD	UV PLD	OT PLD	OT PLD	OT PLD
propagation delay	28 ns	28 ns	18 ns	15 ns	18 ns	15 ns	28 ns	18 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.72 mm	5.08 mm	5.08 mm	5.72 mm	5.72 mm	5.08 mm	4.57 mm	4.57 mm
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	J BEND	J BEND
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	15.24 mm	15.24 mm	15.24 mm	15.24 mm	15.24 mm	15.24 mm	16.5862 mm	16.5862 mm

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