D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
®
HI-201HS
Data Sheet
September 2004
FN3123.4
High Speed, Quad SPST, CMOS Analog
Switch
The HI-201HS is a monolithic CMOS Analog Switch
featuring very fast switching speeds and low ON resistance.
The integrated circuit consists of four independently
selectable SPST switches and is pin compatible with the
industry standard HI-201 switch.
Fabricated using silicon-gate technology and the Intersil
Dielectric Isolation process, this TTL compatible device offers
improved performance over previously available CMOS analog
switches. Featuring maximum switching times of 50ns, low ON
resistance of 50Ω maximum, and a wide analog signal range, the
HI-201HS is designed for any application where improved
switching performance, particularly switching speed, is required.
(A more detailed discussion on the design and application of the
HI-201HS can be found in Application Note AN543.)
Features
•
Pb-free Available as an Option
• Fast Switching Times
- t
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns
- t
OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
• Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . 30Ω
• Pin Compatible with Standard HI-201
• Wide Analog Voltage Range (±15V Supplies) . . . . . . .
±15V
• Low Charge Injection (±15V Supplies) . . . . . . . . . . 10pC
• TTL Compatible
• Symmetrical Switching Analog Current Range . . . . . 80mA
Applications
• High Speed Multiplexing
• High Frequency Analog Switching
Ordering Information
PART NUMBER
HI1-0201HS-2
HI1-0201HS-4
HI1-0201HS-5
HI3-0201HS-5
HI3-0201HS-5Z
(See Note)
HI9P0201HS-5
HI9P0201HS-5Z
(See Note)
HI9P0201HS-9
HI9P0201HS-9Z
(See Note)
TEMP.
RANGE (°C)
-55 to 125
-25 to 85
0 to 75
0 to 75
0 to 75
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
PKG.
DWG. #
F16.3
• Sample and Hold Circuits
• Digital Filters
• Operational Amplifier Gain Switching Networks
F16.3
F16.3
E16.3
E16.3
• Integrator Reset Circuits
Pinout
(Switches Shown For Logic “1” Input)
HI-201HS (CERDIP, PDIP, SOIC)
TOP VIEW
0 to 75
0 to 75
M16.3
M16.3
A
1
OUT1
IN1
1
2
3
4
5
6
7
8
16 A
2
15 OUT2
14 IN2
13 V+
12 NC
11 IN3
10 OUT3
9 A
3
-40 to 85
-40 to 85
M16.3
M16.3
V-
GND
IN4
OUT4
A
4
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-201HS
Functional Diagram
V+
SOURCE
TTL
LOGIC
INPUT
LEVEL
SHIFTER
AND
DRIVER
SWITCH
CELL
GATE
INPUT
TRUTH TABLE
LOGIC
0
1
SWITCH
ON
OFF
GATE
DRAIN
OUTPUT
V-
Schematic Diagrams
TTL/CMOS REFERENCE CIRCUIT
V+
P41
MP42
MP43
MP44
MP45
SWITCH CELL
V+
Q
QN41
QN43
QN42
D41
5V
R42
C48
QP44
QN44
R41
C49
D42
5.6V
QP41
QP42
V-
Q
QN45
V
R1
ANALOG
IN
MP32
MN33
MN31
MP33
MN32
ANALOG
OUT
MP31
MN42
V-
MN44
MN45
2
HI-201HS
Schematic Diagrams
(Continued)
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
M
N46
M
P51
M
P52
Q
N6
Q
N8
Q
N7
I
X1
V
R1
I
X2
Q
N9
M
P3
M
P5
M
P6
M
P4
M
P7
M
P9
M
P10
M
P11
M
P12
M
P8
I
Q
I
X3
I
X4
Q
N1
I
Q
C
1
VA
R
1
Q
N4
Q
P1
V
R1
Q
P5
Q
P4
R
3
R
2
Q
P2
C
FF
I
X1
I
X2
Q
P6
Q
P8
M
N51
REPEAT FOR EACH
LEVEL SHIFTER
M
N52
Q
P7
Q
P9
M
N3
M
N5
M
N4
M
N6
M
N7
M
N9
M
N8
M
N10
M
N13
M
N14
Q
N5
M
N11
V
EE
Q
N2
V
CC
Q
C
2
M
P13
M
P14
M
N12
Q
I
X3
3
HI-201HS
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Input Voltage (One Switch) . . . . . . . (V+) +2.0V to (V-) -2.0V
Peak Current, S or D (Pulse 1ms, 10% Duty Cycle Max) . . . . 50mA
Continuous Current Any Terminal (Except S or D) . . . . . . . . . 25mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
80
20
PDIP Package . . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
100
N/A
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Ranges
HI-201HS-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
HI-201HS-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25
o
C to 85
o
C
HI-201HS-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 75
o
C
HI-201HS-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = +0.8V, GND = 0V,
Unless Otherwise Specified
TEST
CONDITIONS
TEMP
(
o
C)
-2
MIN
TYP
MAX
MIN
-4, -5, -9
TYP
MAX
UNITS
PARAMETER
DYNAMIC CHARACTERISTICS
Switch ON Time, t
ON
Switch OFF Time, t
OFF1
Switch OFF Time, t
OFF2
Output Settling Time
Charge Injection, Q
OFF Isolation
Crosstalk
Input Switch Capacitance, C
S(OFF)
Output Switch Capacitance
C
D(OFF)
C
D(ON)
Digital Input Capacitance, C
A
Drain-To-Source Capacitance, C
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
AL
Input High Threshold, V
AH
(Note 3)
(Note 3)
(Note 3)
To 0.1%
(Note 6)
(Note 4)
(Note 5)
25
25
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
-
30
40
150
180
10
72
86
10
10
30
18
0.5
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
40
150
180
10
72
86
10
10
30
18
0.5
50
50
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
pC
dB
dB
pF
pF
pF
pF
pF
Full
25
Full
-
2.0
2.4
-
-
-
-
-
-
-
200
-
20
-
0.8
-
-
-
500
-
40
-
2.0
2.4
-
-
-
-
-
-
-
200
-
20
-
0.8
-
-
-
500
-
40
V
V
V
µA
µA
µA
µA
Input Leakage Current (Low), I
AL
25
Full
Input Leakage Current (High), I
AH
V
AH
= 4.0V
25
Full
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
S
ON Resistance, r
ON
(Note 2)
Full
25
Full
-15
-
-
-
30
-
+15
50
75
-15
-
-
-
30
-
+15
50
75
V
Ω
Ω
4
京公网安备 11010802033920号
EEWORLD
