a
FEATURES
4.5 ns Propagation Delay
200 ps Maximum Propagation Delay Dispersion
Single +5 V or 5 V Supply Operation
Complementary Matched TTL Outputs
APPLICATIONS
High Speed Line Receivers
Peak Detectors
Window Comparators
High Speed Triggers
Ultrafast Pulse Width Discriminators
Ultrafast
TTL Comparators
AD9696/AD9698
Both devices allow the use of either a single +5 V supply or
±
5 V supplies. The choice of supplies determines the common
mode input voltage range available: –2.2 V to +3.7 V for
±
5 V
operation, +1.4 V to +3.7 V for single +5 V supply operation.
The differential input stage features high precision, with offset
voltages which are less than 2 mV and offset currents less than
1
µA.
A latch enable input is provided to allow operation in ei-
ther sample-and-hold or track-and-hold applications.
The AD9696 and AD9698 are both available as commercial
temperature range devices operating from ambient temperatures
of 0°C to +70°C, and as extended temperature range devices for
ambient temperatures from –55°C to +125°C. Both versions are
available qualified to MIL-STD-883 class B.
Package options for the AD9696 include a 10-pin TO-100 metal
can, an 8-pin ceramic DIP, an 8-pin plastic DIP, and an 8-lead
small outline plastic package. The AD9698 is available in a
16-pin ceramic DIP, a 16-lead ceramic gullwing, a 16-pin plastic
DIP, and a 16-lead small outline plastic package. Military quali-
fied versions of the AD9696 come in the TO-100 can and
ceramic DIP; the dual AD9698 comes in ceramic DIP.
GENERAL DESCRIPTION
The AD9696 and AD9698 are ultrafast TTL-compatible volt-
age comparators able to achieve propagation delays previously
possible only in high performance ECL devices. The AD9696 is
a single comparator providing 4.5 ns propagation delay, 200 ps
maximum delay dispersion and 1.7 ns setup time. The AD9698
is a dual comparator with equally high performance; both de-
vices are ideal for critical timing circuits in such applications as
ATE, communications receivers and test instruments.
FUNCTIONAL BLOCK DIAGRAM
AD9696
AD9696/AD9698 Architecture
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
Q OUTPUT
INPUT
LATCH
GAIN
LEVEL
SHIFT
OUTPUT
LATCH
ENABLE
AD9698
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
#1
Q OUTPUT
Q OUTPUT
Q OUTPUT
#2
NONINVERTING
INPUT
INVERTING
INPUT
LATCH
ENABLE
LATCH
ENABLE
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD9696/AD9698–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage (+V
S
/–V
S
) . . . . . . . . . . . . . . . . . . . . +7 V/–7 V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.4 V
Latch Enable Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +V
S
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range
2
AD9696/AD9698KN/KQ/KR . . . . . . . . . . . . 0°C to +70°C
AD9696/AD9698TQ . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature
KQ/TQ Suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
KN/KR Suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . +300°C
ELECTRICAL CHARACTERISTICS
Parameter
INPUT CHARACTERISTICS
Input Offset Voltage
4
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Capacitance
Input Voltage Range
±
5.0 V
+5.0 V
Common Mode Rejection Ratio
±
5.0 V
+5.0 V
LATCH ENABLE INPUT
Logic “1” Voltage Threshold
Logic “0” Voltage Threshold
Logic “1” Current
Logic “0” Current
DIGITAL OUTPUTS
Logic “1” Voltage (Source 4 mA)
Logic “0” Voltage (Sink 10 mA)
SWITCHING PERFORMANCE
Propagation Delay (t
PD
)
5
Input to Output HIGH
Input to Output LOW
Latch Enable to Output HIGH
Latch Enable to Output LOW
Delta Delay Between Outputs
Propagation Delay Dispersion
20 mV to 100 mV Overdrive
100 mV to 1.0 V Overdrive
Rise Time
10
Fall Time
10
Latch Enable
Pulse Width [t
PW(E)
]
Setup Time (t
S
)
Hold Time (t
H
)
(Supply Voltages = –5.2 V and +5.0 V; load as specified in Note 4,
unless otherwise noted)
0 C to +70 C
AD9696/AD9698
KN/KQ/KR
Min
Typ
Max
1.0
10
16
0.4
3
–2.2
+1.4
80
57
2.0
0.8
10
1
2.7
3.5
0.4
2.7
0.5
3.5
0.4
85
63
+3.7
+3.7
–2.2
+1.4
80
57
2.0
0.8
10
1
85
63
2.0
3.0
55
110
1.0
1.3
–55 C to +125 C
AD9696/AD9698
TQ
Min
Typ
Max
1.0
10
16
0.4
3
+3 7
+3.7
2.0
3.0
55
110
1.0
1.3
Temp
+25°C
Full
Full
+25°C
Full
+25°C
Full
+25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
I
VI
V
I
VI
I
VI
V
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
Units
mV
mV
µV/°C
µA
µA
µA
µA
pF
V
V
dB
dB
V
V
µA
µA
V
V
0.5
Full
Full
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
IV
IV
IV
IV
IV
V
IV
V
V
IV
IV
IV
3.5
3
3
4.5
4.5
6.5
6.5
0.5
100
100
1.85
1.35
2.5
1.7
1.9
7.0
7.0
8.5
8.5
1.5
4.5
4.5
6.5
6.5
0.5
100
100
1.85
1.35
3.5
3
3
2.5
1.7
1.9
7.0
7.0
8.5
8.5
1.5
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
200
200
–2–
REV. B
AD9696/AD9698
Test
Level
0 C to +70 C
AD9696/AD9698
KN/KQ/KR
Min
Typ
Max
–55 C to +125 C
AD9696/AD9698
TQ
Min
Typ
Max
Parameter
POWER SUPPLY
6
Positive Supply Current
7
AD9696
AD9698
Negative Supply Current
8
AD9696
AD9698
Power Dissipation
AD9696 +5.0 V
AD9696
±
5.0 V
AD9698 +5.0 V
AD9698
±
5.0 V
Power Supply Rejection Ratio
9
Temp
Units
(+5.0 V)
mA
mA
(–5.2 V)
mA
mA
mW
mW
mW
mW
dB
dB
Full
Full
Full
Full
Full
Full
Full
Full
+25°C
Full
VI
VI
VI
VI
V
V
V
V
VI
VI
26
52
2.5
5.0
130
146
260
292
70
65
3
4
32
64
4.0
8.0
26
52
2.5
5.0
130
146
260
292
70
65
32
64
4.0
8.0
NOTES
1
Absolute maximum ratings are limiting values, to be applied individually,
and beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances:
AD9696 Metal Can
θ
JA
= 170°C/W
θ
JC
= 50°C/W
AD9696 Ceramic DIP
θ
JA
= 110°C/W
θ
JC
= 20°C/W
AD9696 Plastic DIP
θ
JA
= 160°C/W
θ
JC
= 30°C/W
AD9696 Plastic SOIC
θ
JA
= 180°C/W
θ
JC
= 30°C/W
AD9698 Ceramic DIP
θ
JA
= 90°C/W
θ
JC
= 25°C/W
AD9698 Plastic DIP
θ
JA
= 100°C/W
θ
JC
= 20°C/W
AD9698 Plastic SOIC
θ
JA
= 120°C/W
θ
JC
= 20°C/W
Load circuit has 420
Ω
from +V
S
to output; 460
Ω
from output to ground.
R
S
≤100 Ω.
5
Propagation delays measured with 100 mV pulse; 10 mV overdrive.
6
Supply voltages should remain stable within
±
5% for normal operation.
7
Specification applies to both +5 V and
±
5 V supply operation.
8
Specification applies to only
±
5 V supply operation.
9
Measured with nominal values
±
5% of +V
S
and –V
S
.
10
Although fall time is faster than rise time, the complementary outputs cross at
midpoint of logic swing because of delay on start of falling edge.
Specifications subject to change without notice.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level
Model
AD9696KN
AD9696KR
AD9696KQ
AD9696TQ
AD9696TZ/883B
2
AD9698KN
AD9698KR
AD9698KQ
AD9698TQ
AD9698TZ/883B
3
Package
Plastic DIP
SOIC
Cerdip
Cerdip
Gullwing
Plastic DIP
SOIC
Cerdip
Cerdip
Gullwing
Temperature
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
Package
Option
1
N-8
R-8
Q-8
Q-8
Z-8A
N-16
R-16A
Q-16
Q-16
Z-16
I
II
III
IV
V
VI
– 100% production tested.
– 100% production tested at +25°C, and sample tested at
specified temperatures.
– Sample tested only.
– Parameter is guaranteed by design and characterization
testing.
– Parameter is a typical value only.
– All devices are 100% production tested at +25°C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at temp-
erature exremes for commercial/industrial devices.
NOTES
1
N = Plastic DIP, Q = Cerdip, R = Small Outline (SOIC), Z = Ceramic Leaded
Chip Carrier.
2
Refer to AD9696TZ/883B military data sheet.
3
Refer to AD9698TZ/883B military data sheet.
REV. B
–3–
AD9696/AD9698
PIN CONFIGURATIONS
Q1
OUT
(N/C)
Q1
OUT
(–V
S
)
GROUND (–IN
1
)
LATCH ENABLE 1 (+IN
1
)
N/C (+IN
2
)
–V
S
(–IN
2
)
–IN
1
(+V
S
)
+IN
1
(N/C)
1
2
3
4
5
6
7
8
TOP VIEW
(Not to Scale)
16 Q2
OUT
(LATCH ENABLE 1)
15 Q2
OUT
(GROUND)
14 GROUND (Q1
OUT
)
13
LATCH ENABLE 2 (Q1
OUT
)
+V
S
+IN
–IN
–V
S
1
2
3
4
TOP VIEW
(Not to Scale)
8
7
6
5
Q
OUT
Q
OUT
GROUND
LATCH
ENABLE
12 N/C (Q2
OUT
)
11 +V
S
(Q2
OUT
)
10 –IN
2
(GROUND)
9
+IN
2
(LATCH ENABLE 2)
AD9698KN/KQ/TQ
[AD9698KR/TZ PINOUTS SHOWN IN ( )]
AD9696KN/KR/KQ/TQ/TZ
Name
Q1
OUT
Q1
OUT
GROUND
LATCH
ENABLE 1
Function
One of two complementary outputs. Q1
OUT
will be at logic HIGH if voltage at +IN
1
is greater than voltage at
–IN
1
and LATCH ENABLE 1 is at logic LOW.
One of two complementary outputs. Q1
OUT
will be at logic HIGH if voltage at –IN
1
is greater than voltage at
+IN
1
and LATCH ENABLE 1 is at logic LOW.
Analog and digital ground return. All GROUND pins should be connected together and to a low impedance
ground plane near the comparator.
Output at Q1
OUT
will track differential changes at the inputs when LATCH ENABLE 1 is at logic LOW.
When LATCH ENABLE 1 is at logic HIGH, the output at Q1
OUT
will reflect the input state at the application of
the latch command, delayed by the Latch Enable Setup Time (t
S
). Since the architecture of the input stage (see
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
within 1.7 ns after the latch. This is the Setup Time (t
S
); for guaranteed performance, t
S
must be 3 ns.
No internal connection to comparator.
Negative power supply connection; nominally –5.2 V.
Inverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #2.
Inverting input of differential input stage for Comparator #2.
Positive power supply connection; nominally +5 V.
Output at Q2
OUT
will track differential changes at the inputs when LATCH ENABLE 2 is at logic LOW.
When LATCH ENABLE 2 is at logic HIGH, the output at Q2
OUT
will reflect the input state at the application of
the latch command, delayed by the Latch Enable Setup Time (t
S
). Since the architecture of the input stage (see
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
within 1.7 ns after the latch. This is the Setup Time (t
S
); for guaranteed performance, t
S
must be 3 ns.
One of two complementary outputs. Q2
OUT
will be at logic HIGH if voltage at –IN
2
is greater than voltage at
+IN
2
and LATCH ENABLE 2 is at logic LOW.
One of two complementary outputs. Q2
OUT
will be at logic HIGH if voltage at +IN
2
is greater than voltage at
–IN
2
and LATCH ENABLE 2 is at logic LOW.
N/C
–V
S
–IN
1
+IN
1
+IN
2
–IN
2
+V
S
LATCH
ENABLE 2
Q2
OUT
Q2
OUT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
AD9696/AD9698
LATCH
ENABLE
LATCH
COMPARE
V
OS
TWO DIODES
ABOVE GROUND
t
H
DIFFERENTIAL
INPUT VOLTAGE
V
IN
t
PW (E)
t
S
V
OD
Q
50%
t
PD
t
PD (E)
Q
50%
t
S
– MINIMUM SETUP TIME (Typically 1.7ns)
t
H
– MINIMUM HOLD TIME (Typically 1.9ns)
t
PD
– INPUT TO OUTPUT DELAY
t
PD (E)
– LATCH ENABLE TO OUTPUT DELAY
t
PW (E)
– MINIMUM LATCH ENABLE PULSE WIDTH (Typically 2.5ns)
V
OS
– INPUT OFFSET VOLTAGE
V
OD
– OVERDRIVE VOLTAGE
AD9696/AD9698 Timing Diagram
DIE LAYOUT AND MECHANICAL INFORMATION
THEORY OF OPERATION
Die Dimensions AD9696 . . . . . . . . . . . . . 59×71×15 (± 2) mils
AD9698 . . . . . . . . . . . . 79×109×15 (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4×4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Refer to the block diagram of the AD9696/AD9698 compara-
tors. The AD9696 and AD9698 TTL voltage comparator archi-
tecture consists of five basic stages: input, latch, gain, level shift
and output. Each stage is designed to provide optimal perfor-
mance and make it easy to use the comparators.
The input stage operates with either a single +5-volt supply, or
with a +5-volt supply and a –5.2-volt supply. For optimum
power efficiency, the remaining stages operate with only a single
+5-volt supply. The input stage is an input differential pair
without the customary emitter follower buffers. This configura-
tion increases input bias currents but maximizes the input volt-
age range.
A latch stage allows the most recent output state to be retained
as long as the latch input is held high. In this way, the input to
the comparator can be changed without any change in the out-
put state. As soon as the latch enable input is switched to LOW,
the output changes to the new value dictated by the signal ap-
plied to the input stage.
The gain stage assures that even with small values of input volt-
age, there will be sufficient levels applied to the following stages
to cause the output to switch TTL states as required. A level
shift stage between the gain stage and the TTL output stage
guarantees that appropriate voltage levels are applied from the
gain stage to the TTL output stage.
Only the output stage uses TTL logic levels; this minimum use
of TTL circuits maximizes speed and minimizes power con-
sumption. The outputs are clamped with Schottky diodes to as-
sure that the rising and falling edges of the output signal are
closely matched.
The AD9696 and AD9698 represent the state of the art in high
speed TTL voltage comparators. Great care has been taken to
optimize the propagation delay dispersion performance. This as-
sures that the output delays will remain constant despite varying
levels of input overdrive. This characteristic, along with closely
matched rising and falling outputs, provides extremely consis-
tent results at previously unattainable speeds.
REV. B
–5–
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