MT57V512H36AF-5 datasheet, PDF

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MT57V512H36AF-5: DescriptionDDR SRAM, 512KX36, 2.4ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size374KB，25 Pages; ManufacturerCypress Semiconductor

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MT57V512H36AF-5 Overview

DDR SRAM, 512KX36, 2.4ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

MT57V512H36AF-5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	TBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	2.4 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	DDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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1 MEG x 18, 512 x 36

2.5V V

, HSTL, PIPELINED DDRb2 SRAM

18Mb DDR SRAM

2-Word Burst

Features

•

Fast cycle times

Pipelined, double data rate operation

Single 2.5V ±0.1V power supply (V

)

Separate isolated output buffer supply (V

JEDEC-standard 1.5V to 1.8V (±0.1V) HSTL I/O

User-selectable trip point with V

REF

HSTL programmable impedance outputs

synchronized to optional dual-data clocks

Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

JTAG boundary scan

Fully-static design for reduced-power standby

Clock-stop capability

Common data inputs and data outputs

Low-control ball count

Internally self-timed, registered LATE WRITE cycles

Linear burst order with four-tick burst counter

13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

package

Full data coherency, providing most current data

MT57V1MH18A

MT57V512H36A

Figure 1: 165-Ball FBGA

Table 1:

Valid Part Numbers

DESCRIPTION

1 Meg x 18, DDRb2 SRAM

512K x 36, DDRb2 SRAM

PART NUMBER

MT57V1MH18AF-xx

MT57V512H36AF-xx

Options

• Clock Cycle Timing

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

• Configurations

1 Meg x 18

512K x 36

• Operating Temperature Range

Commercial (0°C

70°C)

• Package

165-ball, 13mm x 15mm FBGA

NOTE:

Marking

-5

-6

-7.5

General Description

MT57V1MH18A

MT57V512H36A

None

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

The Micron

DDR synchronous SRAM employs

high-speed, low-power CMOS designs using an

advanced 6T CMOS process.

The DDR SRAM integrates an 18Mb SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through

registers controlled by an input clock pair (K and K#)

and are latched on the rising edge of K and K#. The

synchronous inputs include all addresses, all data

inputs, active LOW load (LD#) and read/write (R/W#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K#, if C

and C# are not provided.

Asynchronous inputs include impedance match

(ZQ). Synchronous data outputs (Q) are closely

matched to the two echo clocks (CQ and CQ#), which

can be used as data receive clocks. Output data clocks

(C and C#) are also provided for maximum system

clocking and data synchronization flexibility.

18Mb: 2.5V V

, HSTL, Pipelined DDRb2 SRAM

MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03

MT57V512H36AF-5 Related Products

	MT57V512H36AF-5	MT57V512H36AF-7.5	MT57V1MH18AF-6	MT57V512H36AF-6	MT57V1MH18AF-7.5	MT57V1MH18AF-5
Description	DDR SRAM, 512KX36, 2.4ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 512KX36, 3.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 1MX18, 3.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 1MX18, 2.4ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	TBGA,	TBGA,	TBGA,	TBGA,	TBGA,	TBGA,
Contacts	165	165	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	2.4 ns	3.6 ns	3 ns	3 ns	3.6 ns	2.4 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
JESD-609 code	e0	e0	e0	e0	e0	e0
length	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	36	36	18	36	18	18
Humidity sensitivity level	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1
Number of terminals	165	165	165	165	165	165
word count	524288 words	524288 words	1048576 words	524288 words	1048576 words	1048576 words
character code	512000	512000	1000000	512000	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	512KX36	512KX36	1MX18	512KX36	1MX18	1MX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	TBGA	TBGA	TBGA	TBGA	TBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	220	220	220	220	220	220
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V
Minimum supply voltage (Vsup)	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm

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