M464S6453BK0
Revision History
Revision 0.0 (Nov. 2000)
Revision 0.1 (Jan. 2001)
PC100/PC133 512MB SODIMM
• Correted column address information in PIN CONFIGURATION DESCRIPTION.
CA11’is deleted
’
• Defined the input capacitance in CAPACITANCE.
• Redefined the ICC* in DC CHARACTERISTICS.
Revision 0.2 (Feb. 2001)
• Reduced the value of ICC6 for low power 32mA to 24mA
Revision 0.3 (Mar. 2001)
• Redifined the value of Input Capacitance
Revision 0.4 (Jun 2001)
• defined a new product of "-7A"
Rev. 0.4 Jun 2001
M464S6453BK0
M464S6453BK0 SDRAM SODIMM
PC100/PC133 512MB SODIMM
64Mx64 SDRAM SODIMM based on 64Mx8, 4Banks, 8K Refresh,3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M464S6453BK0 is a 64M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M464S6453BK0 consists of eight CMOS 64M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy
substrate. Three 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each SDRAM. The
M464S6453BK0 is a Small Outline Dual In-line Memory Module
and is intended for mounting into 144-pin M46S6453BK0 edge
connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
FEATURE
• Performance range
Part No.
M464S6453BK0-L7A /C7A
M464S6453BK0-L75 /C75
M464S6453BK0-L1H /C1H
M464S6453BK0-L1L /C1L
•
•
•
•
•
Max Freq. (Speed)
133MHz(7.5ns @CL=3)
133MHz(7.5ns @CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,200mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQM0
DQM1
V
DD
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQM4
DQM5
V
DD
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
Pin Front Pin
51
53
55
57
59
DQ14
DQ15
V
SS
NC
NC
52
54
56
58
60
Back
Pin
Front
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
A9
A10/AP
V
DD
DQM2
DQM3
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
**SDA
V
DD
Pin
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
BA1
A11
V
DD
DQM6
DQM7
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
**SCL
V
DD
DQ46 95
DQ47 97
99
V
SS
NC 101
NC 103
105
107
Voltage Key
109
CLK0 62 CKE0 111
64
V
DD
113
V
DD
RAS 66 CAS 115
WE
68 CKE1 117
A12 119
CS0 70
CS1 72 *A13 121
DU
74 CLK1 123
V
SS
V
SS
125
76
NC
NC 127
78
NC
NC 129
80
V
DD
V
DD
131
82
DQ16 84 DQ48 133
DQ17 86 DQ49 135
DQ18 88 DQ50 137
DQ19 90 DQ51 139
V
SS
V
SS
141
92
DQ20 94 DQ52 143
PIN NAMES
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CLK0 ~ CLK1
CS0 ~ CS1
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
SDA
SCL
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Chip select input
Row address strobe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Serial data I/O
Serial clock
Don′t use
No connection
CKE0 ~ CKE1 Clock enable input
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.4 Jun 2001
M464S6453BK0
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
PC100/PC133 512MB SODIMM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
DQ
0
~
63
V
DD
/V
SS
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Rev. 0.4 Jun 2001
M464S6453BK0
FUNCTIONAL BLOCK DIAGRAM
CKE1
CKE0
CS1
CS0
DQM0
PC100/PC133 512MB SODIMM
DQM4
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
U0
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
DQ3
U1
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM6
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
DQ3
U2
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
DQ3
U3
DQ4
DQ5
DQ6
DQ7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
10Ω
DQn
Every DQ pin of SDRAM
•
U0/U4
U1/U5
•
U2/U6
U3/U7
SCL
Serial PD
SA0
SA1 SA2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A0 ~ A12, BA0 & 1
RAS
CAS
WE
CKE0 & 1
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
U4
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
DQ3
U5
DQ4
DQ5
DQ6
DQ7
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
DQ3
U6
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM CS0 CS1 CKE0 CKE1
DQ0
DQ1
DQ2
DQ3
U7
DQ4
DQ5
DQ6
DQ7
SDA
WP
V
DD
Three 0.1 uF X7R 0603 Capacitors
per each SDRAM
Vss
To all SDRAMs
CLK0/1
•
Rev. 0.4 Jun 2001
M464S6453BK0
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
PC100/PC133 512MB SODIMM
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
8
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Symbol
V
DD
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
= 1.4V
±
200 mV)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
OUT
Min
45
45
35
25
35
10
15
Max
90
90
60
45
60
25
30
Unit
pF
pF
pF
pF
pF
pF
pF
Parameter
Input capacitance (A
0
~ A
12
, BA0 ~ BA1)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0 ~ CKE1)
Input capacitance (CLK0 ~ CLK1)
Input capacitance (CS0 ~ CS1)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
Rev. 0.4 Jun 2001