TECHNOLOGY, INC.
2 MEG x 8
EDO DRAM
MT4LC2M8E7
MT4C2M8E7
DRAM
FEATURES
• Industry-standard x8 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
• Single power supply (+3.3V
±0.3V
or +5V
±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 10 column addresses
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View)
28-Pin SOJ
(DA-3)
V
CC
DQ1
DQ2
DQ3
DQ4
WE#
RAS#
NC
A10
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
DQ8
DQ7
DQ6
DQ5
CAS#
OE#
A9
A8
A7
A6
A5
A4
Vss
V
CC
DQ1
DQ2
DQ3
DQ4
WE#
RAS#
NC
A10
A0
A1
A2
A3
Vcc
28-Pin SOJ
(DA-4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
DQ8
DQ7
DQ6
DQ5
CAS#
OE#
A9
A8
A7
A6
A5
A4
Vss
OPTIONS
• Voltages
3.3V
5V
• Refresh Addressing
2,048 (i.e. 2K) Rows
• Packages
Plastic SOJ (300 mil)
Plastic SOJ (400 mil)
Plastic TSOP (300 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
MARKING
LC
C
E7
DJ
DW
TG
-5
-6
None
S
28-Pin TSOP
(DB-3)
V
CC
DQ1
DQ2
DQ3
DQ4
WE#
RAS#
NC
A10
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
DQ8
DQ7
DQ6
DQ5
CAS#
OE#
A9
A8
A7
A6
A5
A4
Vss
Note:
The # symbol indicates signal is active LOW.
2 MEG x 8 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC2M8E7DJ
MT4LC2M8E7DJS
MT4LC2M8E7DW
MT4LC2M8E7DWS
MT4LC2M8E7TG
MT4LC2M8E7TGS
MT4C2M8E7DJ
MT4C2M8E7DJS
MT4C2M8E7DW
MT4C2M8E7DWS
MT4C2M8E7TG
MT4C2M8E7TGS
V
CC
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
REFRESH
2K
2K
2K
2K
2K
2K
2K
2K
2K
2K
2K
2K
PACKAGE
300-SOJ
300-SOJ
400-SOJ
400-SOJ
TSOP
TSOP
300-SOJ
300-SOJ
400-SOJ
400-SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
• Part Number Example: MT4LC2M8E7DJ-5
Note:
The 2 Meg x 8 EDO DRAM base number differentiates the offerings in
one place -
MT4LC2M8E7.
The third field distinguishes the low voltage
offering: LC designates V
CC
= 3.3V and C designates V
CC
= 5V.
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
2 Meg x 8 EDO DRAM
D48.pm5 – Rev. 3/97
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
EDO DRAM
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row address-
defined page boundary. The PAGE cycle is always initiated
with a row address strobed-in by RAS#, followed by a
column address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS# LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS# HIGH terminates the PAGE MODE of
operation, i.e., closes the page.
GENERAL DESCRIPTION
The 2 Meg x 8 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x8 con-
figuration. RAS# is used to latch the row address (first 11
bits). Once the page has been opened by RAS#, CAS# is
used to latch the column address (the latter 10 bits, A10 is
“don’t care”). READ and WRITE cycles are selected with the
WE# input.
A logic HIGH on WE# dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no write will occur, and the data outputs will drive
read data from the accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE# and OE#.
EDO PAGE MODE
The 2 Meg x 8 EDO DRAM provides EDO PAGE MODE,
which is an accelerated FAST PAGE MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS# returns HIGH. EDO allows CAS# precharge
time (
t
CP) to occur without the output data going invalid.
This elimination of CAS# output control allows pipeline
READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO PAGE MODE DRAMs operate like FAST
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS#
V IH
V IL
CAS#
ADDR
DQ V IOH
V IOL
, ,,,,, ,,,,, ,,,,, ,,,,
,, ,,
,
,, , , ,
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
OE#
,,
VALID DATA (A)
t OD
VALID DATA (A)
t OES
t OE
,,, ,,
VALID DATA (B)
t OD
t OEHC
VALID DATA (C)
t OD
,
VALID DATA (D)
t OEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
Figure 1
OE# CONTROL OF DQs
2 Meg x 8 EDO DRAM
D48.pm5 – Rev. 3/97
,
,
,,
,,
DON’T CARE
UNDEFINED
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
EDO DRAM
static low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The optional
Self Refresh feature is initiated by performing a CBR Re-
fresh cycle and holding RAS# LOW for the specified
t
RASS.
Additionally, the “S” option allows for an extended refresh
period of 128ms, or 62.5µs per row if using distributed CBR
Refresh. This refresh rate can be applied during normal
operation, as well as during a standby or BATTERY BACKUP
mode.
The Self Refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh se-
quence, a burst refresh is not required upon exiting
Self Refresh. However, if the DRAM controller utilizes a
RAS#- ONLY or burst refresh sequence, all rows must be
refreshed within the average internal refresh rate, prior to
the resumption of normal operation.
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
Figure 1). WE# can also perform the function of disabling
the output devices under certain conditions, as shown in
Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# high
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last.
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (2,048) are executed within
t
REF (MAX), regardless of sequence. The CBR and Self
Refresh cycles will invoke the internal refresh counter for
automatic RAS# addressing.
An optional Self Refresh mode is also available with the
S version. The “S” option allows the user the choice of a fully
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
RAS#
CAS#
ADDR
DQ V IOH
V IOL
, ,,,,,, ,,, , ,,,,
,, ,,
,
,
, , , ,
,,
,
,,
V IH
V IL
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
V IH
V IL
WE#
,,
VALID DATA (A)
t WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE#
The DQs go to High-Z if WE# falls and, if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
Figure 2
WE# CONTROL OF DQs
2 Meg x 8 EDO DRAM
D48.pm5 – Rev. 3/97
,,
,,
,
,,
DON’T CARE
UNDEFINED
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
EDO DRAM
FUNCTIONAL BLOCK DIAGRAM
WE#
DATA-IN BUFFER
CAS#
8
NO. 2 CLOCK
GENERATOR
DQ8
DATA-OUT
BUFFER
OE#
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLLER
10
DQ1
COLUMN
DECODER
8
1024
8
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
11
ROW
DECODER
1024 x 8
11
ROW
ADDRESS
BUFFERS (11)
11
2048
2048 x 1024 x 8
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
CC
V
SS
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY WRITE
READ WRITE
EDO-PAGE-MODE
READ
EDO-PAGE-MODE
EARLY WRITE
EDO-PAGE-MODE
READ-WRITE
HIDDEN
REFRESH
RAS#-ONLY REFRESH
CBR REFRESH
SELF REFRESH
2 Meg x 8 EDO DRAM
D48.pm5 – Rev. 3/97
DATA-IN/OUT
DQ1-DQ4
High-Z
Data-Out
Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out
Data-Out, Data-In
Data-Out, Data-In
Data-Out
Data-In
High-Z
High-Z
High-Z
RAS#
H
L
L
L
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
Any Cycle
1st Cycle
2nd Cycle
READ
WRITE
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
H→L
CAS#
H→X
L
L
L
H→L
H→L
H→L
H→L
L→H
H→L
H→L
L
L
H
L
L
WE#
X
H
L
H→L
H
H
L
L
H
H→L
H→L
H
L
X
H
H
OE#
X
L
X
L→H
L
L
X
X
L
L→H
L→H
L
X
X
X
X
t
R
t
C
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
n/a
ROW
n/a
ROW
ROW
ROW
X
X
X
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
COL
COL
n/a
X
X
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
EDO DRAM
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Pin Relative to V
SS
:
3.3V ................................................................ -1V to +4.6V
5V ...................................................................... -1V to +7V
Voltage on NC, Inputs or I/O Pins Relative to V
SS
:
3.3V ................................................................ -1V to +5.5V
5V ...................................................................... -1V to +7V
Operating Temperature, T
A
(ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1)
3.3V
PARAMETER/CONDITION
Supply Voltage
Input High Voltage:
Valid Logic 1; all inputs, I/Os and any NC
Input Low Voltage:
Valid Logic 0; all inputs, I/Os and any NC
Input Leakage Current:
Any input at V
IN
(0V
≤
V
IN
≤
V
IH
[MAX]);
all other pins not under test = 0V
Output High Voltage:
I
OUT
= -2mA (3.3V), -5mA (5V)
Output Low Voltage:
I
OUT
= 2mA (3.3V), 4.2mA (5V)
Output Leakage Current:
Any output at V
OUT
(0V
≤
V
OUT
≤
5.5V);
DQ is disabled and in High-Z state
SYMBOL
V
CC
V
IH
V
IL
I
I
MIN
3.0
2.0
-1.0
-2
MAX
3.6
5.5
0.8
2
MIN
4.5
2.4
-1.0
-2
5V
MAX
5.5
V
CC
+1
0.8
2
UNITS
V
V
V
µA
4
NOTES
V
OH
V
OL
I
OZ
2.4
-
-5
-
0.4
5
2.4
-
-5
-
0.4
5
V
V
µA
2 Meg x 8 EDO DRAM
D48.pm5 – Rev. 3/97
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
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