DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD705100
V830
TM
32-BIT MICROCONTROLLER
The
µ
PD705100 (also called V830) is a microcontroller for incorporation use, which belongs to the V830 family
TM
of the NEC original V800 series
TM
microcontrollers. The V830 can achieve high cost-performance for multimedia
equipment, by integrating quick real-time responses, high-speed arithmetic/logical instructions, and functions suitable
for individual applications.
The following user’s manual describes details of the functions of the V830. Be sure to read it before
designing an application system.
V830 User’s Manual, Hardware
: U10064E
V830 User’s Manual, Architecture : U12496E
FEATURES
•
High-performance 32-bit architecture for
incorporation use
• Built-in cache memory
Instruction cache : 4K bytes
Data cache
• Built-in RAM
Instruction RAM
Data RAM
: 4K bytes
: 4K bytes
: 4K bytes
•
16-bit bus fixing function
• 16-bit bus system construction
•
Instructions suitable for variable application
• Sum-of-products operation
• Saturable operation
• Branch prediction
• Concatenation shift
• Block transfer instructions
• One-clock-pitch pipeline structure
• 16-/32-bit instructions
• Separate buses for addresses and data
• 4G-byte linear addresses
• Thirty-two 32-bit general-purpose registers
• Hardware-interlocked register/flag hazard
• 16-level interrupt responses
•
Power-saving mode
•
Maximum operating frequency
• 100 MHz (internal)
• 50/33 MHz (external)
•
CMOS operation, 3.3-V operation
ORDERING INFORMATION
Part number
Package
144-pin plastic LQFP (fine pitch) (20
×
20 mm)
µ
PD705100GJ-100-8EU
The information in this document is subject to change without notice.
Document No. U11483EJ3V0DS00 (3rd edition)
Date Published January 1998 J CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995, 1996
µ
PD705100
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
1.1
Pin Functions .................................................................................................................................
7
7
2.
ADDRESS SPACE .....................................................................................................................
2.1
2.2
Memory Space ................................................................................................................................
I/O Space .........................................................................................................................................
8
8
10
3.
32-BIT BUS MODE .....................................................................................................................
3.1
Relationship between External Accesses and Byte Enable Signals .....................................
13
13
4.
16-BIT BUS MODE .....................................................................................................................
4.1
16-Bit Bus Sizing ...........................................................................................................................
4.1.1
4.1.2
4.2
Byte/halfword access ....................................................................................................
Word access ...................................................................................................................
14
14
14
15
16
Relationship between External Access and Byte Enable Signals .........................................
5.
INTERRUPTS ..............................................................................................................................
5.1
5.2
5.3
Maskable Interrupts .......................................................................................................................
Nonmaskable Interrupts ...............................................................................................................
Reset ................................................................................................................................................
17
17
18
18
6.
CLOCK CONTROLLER .............................................................................................................
6.1
Operation Modes............................................................................................................................
6.1.1
6.1.2
Sleep mode .....................................................................................................................
Stop mode .......................................................................................................................
19
19
19
19
7.
8.
INTERNAL MEMORY .................................................................................................................
REGISTER SETS .......................................................................................................................
8.1
Program Register Set ....................................................................................................................
8.1.1
8.1.2
8.2
General-purpose register set .......................................................................................
Program counter (PC) ...................................................................................................
20
21
21
21
22
23
System Register Set ......................................................................................................................
9.
DATA SETS ................................................................................................................................
9.1
Data Types ......................................................................................................................................
9.1.1
9.1.2
9.2
Integers ...........................................................................................................................
Unsigned integers ..........................................................................................................
24
24
25
25
25
Data Alignment ...............................................................................................................................
10. ADDRESS SPACE .....................................................................................................................
10.1
Addressing Mode ...........................................................................................................................
10.1.1
10.1.2
Instruction addresses ...................................................................................................
Operand addresses .......................................................................................................
26
27
27
28
5
FPGA/CPLD
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