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HYMP125L72CP8D5-C4

Description
240pin Fully Buffered DDR2 SDRAM DIMMs
Categorystorage    storage   
File Size613KB,26 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance
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HYMP125L72CP8D5-C4 Overview

240pin Fully Buffered DDR2 SDRAM DIMMs

HYMP125L72CP8D5-C4 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeDIMM
package instructionDIMM, DIMM240,40
Contacts240
Reach Compliance Codeunknow
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)266 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N240
memory density19327352832 bi
Memory IC TypeDDR DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals240
word count268435456 words
character code256000000
Operating modeSYNCHRONOUS
Maximum operating temperature95 °C
Minimum operating temperature
organize256MX72
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM240,40
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)260
power supply1.5 V
Certification statusNot Qualified
refresh cycle8192
self refreshYES
Maximum supply voltage (Vsup)1.575 V
Minimum supply voltage (Vsup)1.455 V
Nominal supply voltage (Vsup)1.5 V
surface mountNO
technologyCMOS
Temperature levelOTHER
Terminal formNO LEAD
Terminal pitch1 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb C-ver.
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of
each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point
Link Interface at 1.5V power.
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for
handling channel and memory requests to and from the local FBDIMM and for forwarding request to other
FBDIMMs on the memory channel.
FEATURES
240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module
JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.55V +/- 50mV Power Supply
All inputs and outputs are compatible with SSTL_1.8 interface
Built with 1Gb DDR2 SDRAMs in 60ball FBGA
Host interface and AMB component industry standard compliant
MBIST, IBIST test functions
8 Bank architecture
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequential and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
133.35 x 30.35 mm form factor
RoHS compliant
Full DIMM Heat Spreader
This document is a general product description and is subject to change without notice. Hynix Electronics does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Rev 1.0 /June 2008
1

HYMP125L72CP8D5-C4 Related Products

HYMP125L72CP8D5-C4 HYMP125L72CP8D5-Y5
Description 240pin Fully Buffered DDR2 SDRAM DIMMs 240pin Fully Buffered DDR2 SDRAM DIMMs
Is it Rohs certified? conform to conform to
Maker SK Hynix SK Hynix
Parts packaging code DIMM DIMM
package instruction DIMM, DIMM240,40 DIMM, DIMM240,40
Contacts 240 240
Reach Compliance Code unknow unknow
ECCN code EAR99 EAR99
access mode DUAL BANK PAGE BURST DUAL BANK PAGE BURST
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) 266 MHz 333 MHz
I/O type COMMON COMMON
JESD-30 code R-XDMA-N240 R-XDMA-N240
memory density 19327352832 bi 19327352832 bi
Memory IC Type DDR DRAM MODULE DDR DRAM MODULE
memory width 72 72
Number of functions 1 1
Number of ports 1 1
Number of terminals 240 240
word count 268435456 words 268435456 words
character code 256000000 256000000
Operating mode SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 95 °C 95 °C
organize 256MX72 256MX72
Output characteristics 3-STATE 3-STATE
Package body material UNSPECIFIED UNSPECIFIED
encapsulated code DIMM DIMM
Encapsulate equivalent code DIMM240,40 DIMM240,40
Package shape RECTANGULAR RECTANGULAR
Package form MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius) 260 260
power supply 1.5 V 1.5 V
Certification status Not Qualified Not Qualified
refresh cycle 8192 8192
self refresh YES YES
Maximum supply voltage (Vsup) 1.575 V 1.575 V
Minimum supply voltage (Vsup) 1.455 V 1.455 V
Nominal supply voltage (Vsup) 1.5 V 1.5 V
surface mount NO NO
technology CMOS CMOS
Temperature level OTHER OTHER
Terminal form NO LEAD NO LEAD
Terminal pitch 1 mm 1 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 20 20

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