CD-700
Complete VCXO Based Phase
Lock Loop
Features
5 x 7.5 x 2 mm, smallest VCXO PLL available
Output Frequencies to 77.76 MHz
5.0 or 3.3 Vdc operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS outputs
0/70 or –40/85
C
temperature range
Hermetically sealed ceramic SMD package
Product is compliant to RoHS directive
Applications
Frequency Translation
Clock Smoothing, Clock Switching
LO
S
(8)
PHO OPN
(3)
(2)
OPOUT
(1)
VC
(16)
LOSIN
(4)
NRZ Clock recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
DATAIN
(5)
CLKIN
(6)
Phase
Detector
and LOS
OP-Amp
Optional
2
n
Divider
OUT2
(11)
O
VCXO
OUT1
(13)
Synchronous Ethernet
Low jitter PLL’s
Description
The VI CD-700 is a user-configurable crystal
based PLL integrated circuit. It includes a digital
phase detector, op-amp, VCXO and additional
integrated functions for use in digital
synchronization applications. Loop filter software
is available as well SPICE models for circuit
simulation.
RCLK RDATA
(9)
(10)
OPP
(15)
GND
(7)
VDD
(14)
HIZ
(12)
Figure 1. CD-700 Block Diagram
CD-700, VCXO Based PLL
Performance Characteristics
Table 1. Electrical Performance
Parameter
Output Frequency (ordering
option)
OUT1, 5.0 V option
OUT1, 3.3 V option
Supply Voltage
1
+5.0
+3.3
Supply Current
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Transition Times
Rise Time
2
Fall Time
2
Input Logic Levels
Output Logic High
2
Output Logic Low
2
Loss of Signal Indication
Output Logic High
2
Output Logic Low
2
Nominal Frequency on Loss of Signal
Output 1
Output 2
Symmetry or Duty Cycle
3
Out 1
Out 2
RCLK
Absolute Pull Range (ordering
option)
over operating temperature, aging, and
power supply variations
Symbol
Min
1.000
1.000
Typical
Maximum
77.760
77.760
Units
MHz
MHz
V
V
mA
V
V
ns
ns
V
V
V
V
ppm
ppm
%
%
%
ppm
V
DD
4.5
2.97
I
DD
V
OH
V
OL
t
R
t
F
V
IH
V
IL
V
OH
V
OL
2.0
0.5
2.5
0.5
75
75
SYM1
SYM2
RCLK
APR
40/60
45/55
40/60
50
80
100
0.5
0.3
Positive
0.53
0.35
0/70 or –40/85
I
VCXO
1
rad/V
rad/V
C
uA
2.5
0.5
5
5
5.0
3.3
5.5
3.63
63
Test Conditions for APR (+5.0 V option)
Test Conditions for APR (+3.3 V option)
Gain Transfer
Phase Detector Gain
+5V option
+3.3V option
Operating temperature (ordering
option)
Control Voltage Leakage Current
V
C
V
C
4.5
3.0
V
V
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which
these parameters are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
t
R
80
%
t
F
I
DD
14
13
7
15pF
650
1.4V
20
%
V
DD
+
-
.
1F
.01F
I
C
V
C
16
+
-
On Time
Period
1.8k
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RCLK, RDATA
Test Conditions (255°C)
CD-700, VCXO Based PLL
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional
operation is not implied at these or any other conditions in excess of conditions represented in the
operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may
adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Soldering Temperature/Duration
Clock and Data Input Range
Symbol
V
DD
Tstorage
T
PEAK
/ t
P
CLKIN, DATAIN
Ratings
7
-55/125
260 / 40
Gnd-0.5 to V
DD
+0.5
Unit
Vdc
C
C/sec
V
Reliability
The CD-700 is capable of meeting the following qualification tests.
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014, 100% Tested
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the the CD-700, proper precautions should be
taken when handling and mounting. VI employs a Human Body Model (HBM) and a Charged Device
Model (CDM) for ESD susceptibility testing and design protection evaluation. ESD thresholds are
dependent on the circuit parameters used to define the model.
Table 4. Predicted ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
1500 V
1000 V
Conditions
MIL-STD 883, Method 3015
JESD 22-C101
Page 3 of 15
CD-700, VCXO Based PLL
CD-700 Theory of Operation
Phase Detector
The phase detector has two buffered inputs (DATAIN and CLKIN) which are designed to switch at
1.4 volts. DATAIN is designed to accept an NRZ data stream but may also be used for clock signals
which have a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these
outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the power supply
voltage or ground by more than a few hundred millivolts.
The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to
produce a DC signal proportional to the phase between the CLKIN and DATAIN signals (see Figure 4 for
a block diagram and Figure 5 for an open loop transfer curve). This will simplify the PLL design as the
designer does not have to filter narrow pulse signals to a DC level. Under locked conditions the rising
edge of CLKIN will be centered in the middle of the DATAIN signal (see Figure 6).
The phase detector gain is 0.53V/rad x data density for 5volt operation and 0.35V/rad x data density for
3.3 volt operation. Data density is equal to 1.0 for clock signals and is system dependent on coding and
design for NRZ signals, but 0.25 could be used as a starting point for data density.
The phase detector output is a DC signal for DATAIN frequencies greater than 1 MHz but produces
significant ripple when inputs are less than 200 kHz. Additional filtering is required for lower input
frequencies applications such as 8kHz (see Figures 8 and 9 as examples).
Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC
gain, so under normal locked conditions and input frequencies >1 MHz, PHO will be about V
DD
/2 and will
not vary significantly with changes in input frequency (within lock range). The control voltage (pin 16) will
vary according to the input frequency offset, but PHO will remain relatively constant.
Data In
(pin 5)
D
Clock In
(pin 6)
Q
1
30 k
20 k
D
Q
2
PHO
(pin 3)
Gain = V
DD
/ 2
Gain = 2 / 3
Figure 4. Simplified Phase Detector Block Diagram
Page 4 of 15
CD-700, VCXO Based PLL
V
DD
V
d
V
DD
/2
0
Relative
Phase (
e
)
0V
Gain Slope = V
DD
/ 2
Figure 5. Open Loop Phase Detector Transfer Curve
Recovered Clock and Data Alignment Outputs
The CD-700 is designed to recover an embedded clock from an NRZ data signal and retime it with a data
pattern. In this application, the VCXO frequency is exactly the same frequency as the NRZ data rate and
the outputs are taken off Pin 9 (RCLK), and Pin 10 (RDATA). Under locked conditions, the falling edge of
RCLK is centered in the RDATA pattern. Also, there is a 1.5 clock cycle delay between DATAIN and
RDATA. Figure 6 shows the relationship between the DATAIN, CLKIN, RDATA and RCLK.
Data In
DATAIN
Clock In
CLKIN
Recovered Data
RDATA
Recovered Clock
RCLK
Data1
Figure 6. Clock and Data Timing Relationships for the NRZ data
Other RZ encoding schemes such as Manchester or AMI can be accomodated by using a CD-700 at
twice the baud rate.
Loss of Signal, LOS and LOSIN
The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is
normally a logic low and is set to a logic high after 256 consecutive clock periods on CLKIN with no
detected DATAIN transitions. This signal can be used to either flag external alarm circuits and/or drive the
CD-700’s LOSIN input. When LOSIN is set to a logic high, the VCXO control voltage (pin 16) is switched
to an internal voltage which sets OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS automatically
closes the op amp feedback which means the op-amp is a unity gain buffer and will produce a DC voltage
equal to the +op amp voltage (pin 15), usually V
DD
/2.
VCXO and Absolute Pull Range (APR) Specification
Page 5 of 15
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