W3E64M16S-250SBM datasheet, PDF

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W3E64M16S-250SBM: DescriptionDDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60; Categorystorage storage; File Size947KB，16 Pages; ManufacturerMercury Systems Inc

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W3E64M16S-250SBM Overview

DDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60

W3E64M16S-250SBM Parametric

Parameter Name	Attribute value
Maker	Mercury Systems Inc
package instruction	BGA,
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.8 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
length	12.5 mm
memory density	1073741824 bi
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	64MX16
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	2.56 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	10 mm

W3E64M16S-250SBM Preview

W3E64M16S-XSBX

64Mx16 DDR SDRAM

FEATURES



DDR SDRAM rate = 200, 250, 266, 333**



Package:

• 60 Plastic Ball Grid Array (PBGA), 10 x 12.5mm



1Gb upgrade to 512Mb 60 FBGA SDRAM



2.5V ±0.2V core power supply



2.5V I/O (SSTL_2 compatible)



Differential clock inputs (CK and CK#)



Commands entered on each positive CK edge



Internal pipelined double-data-rate (DDR) architecture; two

data accesses per clock cycle



Programmable Burst length: 2,4 or 8



Bidirectional data strobe (DQS) transmitted/received with

data, i.e., source-synchronous data capture (one per byte)



DQS edge-aligned with data for READs; center-aligned with

data for WRITEs



DLL to align DQ and DQS transitions with CLK



Four internal banks for concurrent operation



Data mask (DM) pins for masking write data (one per byte)



Auto precharge option



Auto Refresh and Self Refresh Modes



Commercial, Industrial and Military Temperature ranges



Organized as 64M x 16



Weight: W3E64M16S-XSBX — 1.0 grams typical

GENERAL DESCRIPTION

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,

dy nam ic ran dom-access, memory using 2 chips containing

536,870,912 bits. Each chip is internally conﬁgured as a quad-

bank DRAM.

The 128MB DDR SDRAM uses a double data rate architecture to

achieve high-speed operation. The double data rate architecture is

essentially a 2n-prefetch architecture with an interface designed to

transfer two data words per clock cycle at the I/O pins. A single read

or write access for the 256MB DDR SDRAM effectively consists of

a single 2n-bit wide, one-clock-cycle data transfer at the internal

DRAM core and two corresponding n-bit wide, one-half-clock-cycle

data transfers at the I/O pins.

A bi-directional data strobe (DQS) is transmitted externally, along

with data, for use in data capture at the receiver.strobe transmitted

by the DDR SDRAM during READs and by the memory controller

during WRITEs. DQS is edge-aligned with data for READs and

center-aligned with data for WRITEs. Each chip has two data

strobes, one for the lower byte and one for the upper byte.

The 128MB DDR SDRAM operates from a differential clock (CK

and CK#); the crossing of CK going HIGH and CK going LOW will

be referred to as the positive edge of CK. Commands (address

and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented;

accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses begin

with the registration of an ACTIVE command, which is then followed

by a READ or WRITE command. The address bits registered

coincident with the ACTIVE command are used to select the bank

and row to be accessed. The address bits registered coincident

with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE

burst lengths of 2, 4, or 8 locations. An auto precharge function may

be enabled to provide a self-timed row precharge that is initiated

at the end of the burst access.

The pipelined, multibank architecture of DDR SDRAMs allows for

concurrent operation, thereby providing high effective bandwidth

by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-saving

power-down mode.

* This product is subject to change without notice.

** For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature

CL = 3.

BENEFITS



53% SPACE SAVINGS vs. 1-1GbTSOP

• 50% Space Savings vs 2 - 512Mb FPBGA



Reduced part count

• 50% I/O reduction vs FPBGA

• 9% I/O reduction vs TSOP



Reduced trace lengths for lower parasitic capacitance



Suitable for hi-reliability applications

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

March 2016

Rev. 10

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3E64M16S-XSBX

DENSITY COMPARISONS

TSOP Approach (mm)

11.9

W3E64M16S-XSBX

22.3

64Mx16

TSOP

12.5

W3E64M16S-XSBX

Area

I/O Count

265mm

66 pins

125mm

60 Balls

53%

CSP Approach (mm)

10.0

FBGA

10.0

FBGA

W3E64M16S-XSBX

12.5

W3E64M16S-XSBX

50%

Area

I/O Count

2 x 125mm2 = 250mm

2 x 60 balls = 120 balls

125mm

60 Balls

FUNCTIONAL DESCRIPTION

Read and write accesses to the DDR SDRAM are burst oriented;

accesses start at a selected location and continue for a pro-

grammed number of locations in a programmed sequence. Ac-

cesses begin with the registration of an ACTIVE command which

is then followed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command are used to

select the bank and row to be accessed (BA0 and BA1 select the

bank, A0-12 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the starting

column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized.

The following sections provide detailed information covering de-

vice initialization, register deﬁnition, command descriptions and

device operation.

INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predeﬁned

manner. Operational procedures other than those speciﬁed may

result in undeﬁned operation. Power must

ﬁ

rst be applied to V

and V

CCQ

simultaneously, and then to V

REF

(and to the system V

must be applied after V

CCQ

to avoid device latch-up, which may

cause permanent damage to the device. V

REF

can be applied any

time after V

CCQ

but is expected to be nominally coincident with V

Except for CKE, inputs are not recognized as valid until after V

REF

is applied. CKE is an SSTL_2 input but will detect an LVCMOS

LOW level after V

is applied. After CKE passes through V

, it

will transition to an SSTL_2 signal and remain as such until power

is cycled. Maintaining an LVCMOS LOW level on CKE during

power-up is required to ensure that the DQ and DQS outputs will

be in the High-Z state, where they will remain until driven in normal

operation (by a read access). After all power supply and reference

voltages are stable, and the clock is stable, the DDR SDRAM

requires a 200μs delay prior to applying an executable command.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

March 2016

Rev. 10

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3E64M16S-XSBX

BALL ASSIGNMENT (TOP VIEW) 60 BALL FBGA

x16 (Top View)

SSQ

DQ14

DQ12

DQ10

DQ8

REF

DQ15

CCQ

SSQ

CCQ

SSQ

A12

A11

DQ13

DQ11

DQ9

UDQS

UDM

CK#

CKE

DQ2

DQ4

DQ6

LDQS

LDM

WE#

RAS#

BA1

DQ0

SSQ

CCQ

SSQ

CCQ

CAS#

CS#

BA0

A10

CCQ

DQ1

DQ3

DQ5

DQ7

DNU

NOTES: Refer to note 41, page 13 for power/ground pins conﬁguration.

DNU = Do Not Use; to be left unconnected for future upgrades.

NC = Not Connected Internally.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

March 2016

Rev. 10

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3E64M16S-XSBX

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

WE#

RAS#

CAS#

WE#

REF

A0-12

BA0-1

CLK

CLK#

CKE

CS#

DQM

DQS

RAS# CAS#

DQ0

REF

A0-12

BA0-1

CK#

CKE

CS#

LDM

LDQS

64Mx8

DQ7

WE# RAS# CAS#

REF

A0-12

BA0-1

CLK

CLK#

CKE

CS#

DQM

DQS

DQ0

DQ8

64Mx8

UDM

UDQS

DQ7

DQ15

MODE REGISTER

The Mode Register is used to deﬁne the speciﬁc mode of operation

of the DDR SDRAM. This deﬁnition includes the selection of a

burst length, a burst type, a CAS latency, and an operating mode,

as shown in Figure 3. The Mode Register is programmed via the

MODE REGISTER SET command (with BA0 = 0 and BA1 = 0)

and will retain the stored information until it is programmed again

or the device loses power. (Except for bit A8 which is self clearing).

Reprogramming the mode register will not alter the contents of

the memory, provided it is performed correctly. The Mode Register

must be loaded (reloaded) when all banks are idle and no bursts

are in progress, and the controller must wait the speci

ﬁ

ed time

before initiating the subsequent operation. Violating either of these

requirements will result in unspeci

ﬁ

ed operation.

Mode register bits A0-A2 specify the burst length, A3 speci

ﬁ

es the

type of burst (sequential or interleaved), A4-A6 specify the CAS

latency, and A7-A12 specify the operating mode.

locations that can be accessed for a given READ or WRITE

command. Burst lengths of 2, 4 or 8 locations are available for

both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or

incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns

equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst will

wrap within the block if a boundary is reached. The block is uniquely

selected by A1-Ai when the burst length is set to two; by A2-Ai

when the burst length is set to four (where Ai is the most signiﬁcant

column address for a given conﬁguration); and by A3-Ai when

the burst length is set to eight. The remaining (least signiﬁcant)

address bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to both READ

and WRITE bursts.

BURST TYPE

Accesses within a given burst may be programmed to be either

sequential or interleaved; this is referred to as the burst type and

is selected via bit M3.

The ordering of accesses within a burst is determined by the burst

length, the burst type and the starting column address, as shown

in Table 1.

BURST LENGTH

Read and write accesses to the DDR SDRAM are burst oriented,

with the burst length being programmable, as shown in Figure

3. The burst length determines the maximum number of column

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

March 2016

Rev. 10

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3E64M16S-XSBX

FIGURE 3 – MODE REGISTER DEFINITION

Address Bus

All other combinations of values for A7-A12 are reserved for future

use and/or test modes. Test modes and reserved states should

not be used because unknown operation or incompatibility with

future versions may result.

TABLE 1 – BURST DEFINITION

Mode Register (Mx)

Operating Mode

CAS Latency

Burst Length

* M14 and M13

(BA0 and BA1 must be

"0, 0" to select

the base mode register

(vs. the extended

mode register).

Burst

Length

Burst Length

Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential Type = Interleaved

0-1

1-0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1

1-0

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

M2 M1 M0

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

M3 = 0

Reserved

M3 = 1

Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

CAS Latency

Reserved

2.5

Reserved

M12

M11

M10

M6-M0

Valid

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

READ LATENCY

The READ latency is the delay, in clock cycles, between the

registration of a READ command and the availability of the

ﬁ

rst bit

of output data. The latency can be set to 2 or 2.5 clocks.

If a READ command is registered at clock edge n, and the latency

is m clocks, the data will be available by clock edge n+m. Table

2 below indicates the operating frequencies at which each CAS

latency setting can be used.

Reserved states should not be used as unknown operation or

incompatibility with future versions may result.

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column

within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column

within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column

within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

EXTENDED MODE REGISTER

The extended mode register controls functions beyond those

controlled by the mode register; these additional functions are DLL

enable/disable, output drive strength, and QFC. These functions

are controlled via the bits shown in Figure 5. The extended mode

to the mode register (with BA0 = 1 and BA1 = 0) and will retain the

stored information until it is programmed again or the device loses

power. The enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode register (BA0/

BA1 both LOW) to reset the DLL.

OPERATING MODE

The normal operating mode is selected by issuing a MODE

and bits A0-A6 set to the desired values. A DLL reset is initiated

by issuing a MODE REGISTER SET command with bits A7 and

A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to

the desired values. Although not required, JEDEC speciﬁcations

recommend when a LOAD MODE REGISTER command is issued

to reset the DLL, it should always be followed by a LOAD MODE

TABLE 2 – CAS LATENCY

ALLOWABLE OPERATING FREQUENCY (MHz)

CAS LATENCY

CAS LATENCY = 2

= 2.5

CAS LATENCY = 3

≤

100

—

≤

100

≤

125

—

≤

100

≤

133

—

≤

100

≤

166

≤

166

SPEED

-200

-250

-266

-333 IND

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

March 2016

Rev. 10

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

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W3E64M16S-250SBM Related Products

	W3E64M16S-250SBM	W3E64M16S-250SBI	W3E64M16S-333SBM	W3E64M16S-333SBI	W3E64M16S-266SBI	W3E64M16S-200SBI	W3E64M16S-200SBM	W3E64M16S-266SBM
Description	DDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60	DDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60	DDR DRAM, 64MX16, 0.7ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60	DDR DRAM, 64MX16, 0.7ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60	DDR DRAM, 64MX16, 0.75ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60	DDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60	DDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60	DDR DRAM, 64MX16, 0.75ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60
Maker	Mercury Systems Inc	Mercury Systems Inc	Mercury Systems Inc	Mercury Systems Inc	Mercury Systems Inc	Mercury Systems Inc	Mercury Systems Inc	Mercury Systems Inc
package instruction	BGA,	BGA,	BGA,	BGA,	BGA,	BGA,	BGA,	BGA,
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown	unknown	unknown	unknow
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.8 ns	0.8 ns	0.7 ns	0.7 ns	0.75 ns	0.8 ns	0.8 ns	0.75 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60
length	12.5 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm
memory density	1073741824 bi	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1
Number of terminals	60	60	60	60	60	60	60	60
word count	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words
character code	64000000	64000000	64000000	64000000	64000000	64000000	64000000	64000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	125 °C	85 °C	125 °C	85 °C	85 °C	85 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-40 °C	-55 °C	-40 °C	-40 °C	-40 °C	-55 °C	-55 °C
organize	64MX16	64MX16	64MX16	64MX16	64MX16	64MX16	64MX16	64MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	240	240	240	240	240	240	240	240
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.56 mm	2.56 mm	2.56 mm	2.56 mm	2.56 mm	2.56 mm	2.56 mm	2.56 mm
self refresh	YES	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	INDUSTRIAL	MILITARY	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	MILITARY	MILITARY
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30
width	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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